74LVC573A

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Product data sheet

Rev. 5 — 19 February 2013

5 of 20

NXP Semiconductors

74LVC573A

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

6.

Functional description

[1]

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition

Z = high-impedance OFF-state

7.

Limiting values

[1]

The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2]

The output voltage ratings may be exceeded if the output current ratings are observed.

[3]

For SO20 packages: above 70

C the value of P

For (T)SSOP20 packages: above 60

C the value of P

For DHVQFN20 and DHXQFN20 packages: above 60

C the value of P

Table 3.

Functional table[1]

Operating modes

Input

Internal latch Output

OE

LE

Dn

Qn

Enable and read register

(transparent mode)

LH

L

L

L

LH

H

H

H

Latch and read register

L

L

l

L

L

LL

h

H

H

Latch register and disable outputs

H

L

l

L

Z

HL

h

H

Z

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

0.5

+6.5

V

input clamping current

50

-

mA

input voltage

[1]

0.5

+6.5

V

output clamping current

-

50

mA

output voltage

[2]

0.5

V

output current

-

50

mA

supply current

-

100

mA

ground current

100

-

mA

storage temperature

65

+150

C

total power dissipation

[3] -500

mW