6-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR

2

REVISION A 09/24/14

9FGU0631 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

40 39 38 37 36 35 34 33 32 31

vSS_EN_tri 130 vOE3#

XIN/CLKIN_25 229 DIF3#

X2 328 DIF3

VDDXTAL1.5 427 VDDIO

VDDREF1.5 526 VDDA1.5

vSADR/REF1.5 625 NC

NC 724 vOE2#

GNDDIG 823 DIF2#

SCLK_3.3 922 DIF2

SDATA_3.3 10

21 vOE1#

11 12 13 14 15 16 17 18 19 20

v

prefix indicates internal 120KOhm pull down resistor

^

prefix indicates internal 120KOhm pull up resistor

9FGU0631

Paddle is GND

40-pin VFQFPN, 5x5 mm, 0.4mm pitch

SADR

Address

0

1101000

1

1101010

State of SADR on first application

of CKPWRGD_PD#

+

Read/Write Bit

x

x

OEx#

True O/P

Comp. O/P

0

X

X

Low

Low

1

1

0

Running

Running

Running

1

0

1

Low

Low

Low

REF

CKPWRGD_PD#

SMBus

OE bit

DIFx

1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when

CKPWRG_PD# is low, REF is Low.

Pin Number

VDD

VDDIO

GND

441

XTAL OSC

5

41

REF Power

11

8

Digital (dirty)

Power

12,17,27,32,39

41

DIF outputs

26

41

PLL Analog

Description