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BQ24266 Datasheet(PDF) 5 Page - Texas Instruments |
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BQ24266 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 41 page  bq24266 www.ti.com SLUSBY5F – JUNE 2014 – REVISED AUGUST 2015 Pin Functions PIN PIN I/O DESCRIPTION NAME NUMBER AGND 20 – Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. BAT Battery Connection. Connect to the positive pin of the battery. Bypass BAT to GND with at least 1 μF of ceramic 8, 9 I/O capacitance. See Application section for additional details. BGATE External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during high 11 O impedance mode or when no input is connected. If no external FET is required, leave BGATE disconnected. Do not connect BGATE to GND. BOOT High Side MOSFET Gate Driver Supply. Connect 0.033µF of ceramic capacitance (voltage rating > 10V) from 2 I BOOT to SW to supply the gate drive for the high side MOSFET. CE IC Charge Enable Input. Drive CE high to place the part to disable charge. Drive CE low for normal operation. 4 I CE is pulled low internally with 100k Ω. CHG Charge Status Open Drain Output. CHG is pulled low when a charge cycle starts and remains low while 13 O charging. CHG is high impedance when the charging terminates and when when no supply exists. DRV Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND 3 O with at least a 2.2µF, 10V, X5R or better capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP). IN DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass IN to 18, 19 I PGND with at least a 4.7 μF of ceramic capacitance. ISET Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast charge current. 12 I The charge current is programmable from 500mA to 3A. IUSB1 17 I USB Input Current Limit Programming Inputs. IUSB1, IUSB2 and IUSB3 program the input current limit for the USB input. USB2.0 and USB3.0 current limits are available for easy implementation of these standards. Table 1 IUSB2 16 I shows the settings for these inputs. IUSB3 14 I PG Power Good Open Drain output. PG is pulled low wehn a valid supply is connected. A valud supply is between 10 O VBAT+VSLP and VOVP. The output is high impedance if the supply is not in this range. PGND 21,22 – Ground pin. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. PMID High Side Bypass Connection. Connect at least 1µF of ceramic capacitance from PMID to PGND as close to the 1 I PMID and PGND pins as possible. SW Inductor Connection. Connect to the switched side of the external inductor. The inductance must be between 23, 24 O 1.5µH and 2.2µH. SYS System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk 6, 7 I capacitors. Bypass SYS locally with at least 10 μF of ceramic capacitance. The SYS rail must have at least 20µF of total capacitance for stable operation. See Application section for additional details. TS Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. Pull TS high to VDRV 5 I to disable the TS function if unused. See the NTC Monitor section for more details on operation and selecting the resistor values. VDPM Input DPM Programming Input. Connect a resistor divider from IN to GND with VDPM connected to the center tap to program the Input Voltage based Dynamic Power Management (VIN_DPM) threshold. The input current is 15 I reduced to maintain the supply voltage at VIN_DPM. See the Input Voltage based Dynamid Power Management section for a detailed explanation. Thermal PAD There is an internal electrical connection between the exposed thermal pad and the PGND pin of the device. The – – thermal pad must be connected to the same potential as the PGND pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. PGND pin must be connected to ground at all times. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 |
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