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82P33831 Datasheet(PDF) 4 Page - Integrated Device Technology |
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82P33831 Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 13 page  82P33831 SHORT FORM DATA SHEET SYNCHRONIZATION MANAGEMENT UNIT FOR IEEE 1588 AND 10G/40G SYNCHRONOUS ETHERNET 4 REVISION 2 12/08/14 FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram Control and Status Registers OutDiv OutDiv I2C Slave JTAG I2C Master Reference monitors Reference selection Frac-N input dividers SYS PLL DPLL2 / DCO2 APLL1 APLL2 OutDiv OutDiv OutDiv DPLL1 / DCO1 OUT3p/n OUT4p/n OUT5p/n OUT6p/n OUT7 System Clock LOS0 / XO_FREQ0 LOS1 / XO_FREQ1 LOS2 / XO_FREQ2 LOS3 ex_sync module Composite Clocks IN1(CC) IN2(CC) IN5(P/N) IN6(P/N) IN7(P/N) IN3(P/N) IN4(P/N) IN8(P/N) IN9 IN10 IN11 IN12 IN13 IN14 FRSYNC_8K_1PPS MFRSYNC_2K_1PPS Crystal OutDiv OUT1 OutDiv OUT2 OutDiv OutDiv OUT11p/n OUT12p/n APLL3 (VCXO) OutDiv OutDiv OUT9 OUT10 OUT8 Composite Clock DPLL3 ToD/ Time Accumulator ToD/ Time Accumulator |
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