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MAX4022ESD Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX4022ESD Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 12 page Low-Cost, High-Speed, Single-Supply, Gain of +2 Buffers with Rail-to-Rail Outputs in SOT23 _______________________________________________________________________________________ 9 Input Voltage Range and Output Swing The input range for the MAX4014 family extends from (VEE - 100mV) to (VCC - 2.25V). Input ground sensing increases the dynamic range for single-supply applica- tions. The outputs drive a 2k Ω load to within 60mV of the power-suply rails. With heavier loads, the output swing is reduced as shown in the Electrical Character- istics and the Typical Operating Characteristics. As the load increases, the input range is effectively limited by the output-drive capability, since the buffers have a fixed voltage gain of +2 or -1. For example, a 50 Ω load can typically be driven from 40mV above VEE to 1.6V below VCC, or 40mV to 3.4V when operating from a single +5V supply. If the buffer is operated in the noninverting, gain of +2 configuration with the inverting input grounded, the effective input voltage range becomes 20mV to 1.7V, instead of the -100mV to 2.75V indicated by the Electrical Character- istics. Beyond the effective input range, the buffer out- put is a nonlinear function of the input, but it will not undergo phase reversal or latchup. Enable The MAX4019 has an enable feature (EN_) that allows the buffer to be placed in a low-power state. When the buffers are disabled, the supply current will not exceed 550µA per buffer. As the voltage at the EN_ pin approaches the negative supply rail, the EN_ input current rises. Figure 2 shows a graph of EN_ input current versus EN_ pin voltage. Figure 3 shows the addition of an optional resistor in series with the EN pin, to limit the magnitude of the cur- rent increase. Figure 4 displays the resulting EN pin input current to voltage relationship. 20 -160 0 100 300 500 -100 -120 0 VIL (mV ABOVE VEE) 200 400 -60 -140 -20 -40 -80 Figure 2. Enable Logic-Low Input Current vs. Enable Logic- Low Threshold OUT IN- EN_ IN+ 10k ENABLE MAX40_ _ 500 Ω 500 Ω Figure 3. Circuit to Reduce Enable Logic-Low Input Current 0 -10 0 100 300 500 -7 -8 -1 VIL (mV ABOVE VEE) 200 400 -3 -5 -9 -2 -4 -6 Figure 4. Enable Logic-Low Input Current vs. Enable Logic- Low Threshold with 10k Ω Series Resistor |
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