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STC5420 Datasheet(PDF) 2 Page - Connor-Winfield Corporation |
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STC5420 Datasheet(HTML) 2 Page - Connor-Winfield Corporation |
2 / 70 page Page 2 of 70 Rev:2.0 Date: September 28, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5420 Synchronous Clock for SETS Data sheet Table of Contents STC5420 Pin Diagram (Top View) .................................................................................................................... 5 STC5420 Pin Description .................................................................................................................................. 6 Register Map ..................................................................................................................................................... 9 Master Clock Frequency .................................................................................................................................. 12 Input and Output Frequencies ......................................................................................................................... 13 Input Frequencies .................................................................................................................................... 13 Auto-Detect Acceptable Input Frequencies ...................................................................................... 13 Manually Acceptable Input Frequencies ..........................................................................................13 Clock Output Frequencies ....................................................................................................................... 14 Clock Output Jitter ................................................................................................................................... 15 General Description ......................................................................................................................................... 16 Application ............................................................................................................................................... 16 Overview .................................................................................................................................................. 16 Chip Master Clock .................................................................................................................................... 16 Reference Inputs ...................................................................................................................................... 16 Timing Generators and Operation Modes ................................................................................................ 16 Phase Synchronization ............................................................................................................................ 17 Clock Outputs .......................................................................................................................................... 17 Redundant Designs ................................................................................................................................. 17 Control Interfaces ..................................................................................................................................... 18 Field Upgradability ................................................................................................................................... 18 Advantage and Performance ................................................................................................................... 18 Detailed Description ......................................................................................................................................... 19 Chip Master Clock .................................................................................................................................... 19 Freerun Clock .......................................................................................................................................... 19 Operation Mode ....................................................................................................................................... 19 PLL Event In ............................................................................................................................................ 20 Frequency and Phase Transients ............................................................................................................ 20 Frequency Transients ....................................................................................................................... 20 Phase Transients ............................................................................................................................. 20 History of Fractional Frequency Offset .................................................................................................... 20 Short-Term History ........................................................................................................................... 20 Long-Term History ............................................................................................................................ 21 Device Holdover History ................................................................................................................... 21 User-Specified History ...................................................................................................................... 21 Phase-Locked Loop Status Details .......................................................................................................... 21 Reference Inputs Details .......................................................................................................................... 22 Acceptable Frequency and Frequency Offset Detection .................................................................. 22 Activity Monitoring ............................................................................................................................ 22 Input Qualification ............................................................................................................................ 23 Automatic Reference Election Mechanism ...................................................................................... 23 Automatic Reference Selection ........................................................................................................ 24 Manual Reference Selection Mode .................................................................................................. 24 Hard-wired Manual Reference Selection ......................................................................................... 24 Clock Outputs Details .............................................................................................................................. 24 Clock Synthesizers ........................................................................................................................... 24 Clock Generators ............................................................................................................................. 25 Clock Output Phase Alignment ........................................................................................................ 25 Synthesizer Skew Programming ...................................................................................................... 25 |
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