BLC8G20LS-310AV

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Product data sheet

Rev. 2 — 6 May 2015

6 of 15

NXP Semiconductors

BLC8G20LS-310AV

Power LDMOS transistor

[1]

[2]

at 3 dB gain compression.

7.4 Test circuit

Table 13.

Typical impedance of peak device at 1 : 1 load

f



D

[2]

(MHz)

(

)

(

)

(dBm)

(%)

(dB)

Maximum power load

1930

1.1

 j4.9

1.7

 j4.9

231.2

51.9

16.6

1962

1.4

 j4.1

1.6

 j4.7

217.8

53.0

17.3

1995

1.8

 j4.4

1.6

 j4.5

215.3

57.1

17.9

Table 14.

Off-state impedances of peak device

f

(MHz)

(

)

1930

0.6 + j1.9

1962

0.6 + j2.2

1995

0.6 + j2.5

Printed-Circuit Board (PCB): Rogers RO4350B; thickness = 0.508 mm;

thickness copper plating = 35

m. See Table 15 for a list of components.

Fig 2.

Component layout for test circuit