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MAX4358ECE Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX4358ECE Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 43 page 32 x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers ______________________________________________________________________________________ 11 SWITCHING CHARACTERISTICS ((VCC - VEE) = +4.5V to +10.5V, VDD = +2.7V to +5.5V, DGND = AGND = 0, VIN_ = VOSDFILL_ = 0 for dual supplies, VIN_ = VOSDFILL_ = +1.75V for single supply, RL = 150Ω to AGND, CL = 100pF, AV = +1V/V, and TA = TMIN - TMAX, unless otherwise noted. Typical values are at TA = +25°C. ) Note 1: Associated output voltage may be determined by multiplying the input voltage by the specified gain (AV) and adding output offset voltage. Gain is specified for IN_ and OSDFILL_ signal paths. Note 2: Logic level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A3–A0, MODE, AOUT, and OSDKEY_. Note 3: Switching transient settling time is guaranteed by the settling time (tS) specification. Switching transient is a result of updat- ing the switch matrix. Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V. Note 5: All devices are 100% production tested at +25°C. Specifications over temperature limits are guaranteed by design. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delay: UPDATE to Video Out tPdUdVo VIN = 0.5V step 200 450 ns Delay: UPDATE to AOUT tPdUdAo MODE = 0, time to AOUT = low after UPDATE = low 30 200 ns VDD = +5V 40 Delay: OSDKEY_ to Output tPdOkVo/ tPdOfVo VOUT = 0.5V step VDD = +3V 60 ns Delay: SCLK to DOUT Valid tPdDo Logic state change in DOUT on active SCLK edge 30 200 ns Delay: Output Disable tPdHOeVo VOUT = 0.5V, 1kΩ pulldown to AGND 300 800 ns Delay: Output Enable tPdLOeVo Output disabled, 1k Ω pulldown to AGND, VIN = 0.5V 200 800 ns Setup: CE to SCLK tSuCe 100 ns Setup: DIN to SCLK tSuDi 100 ns Hold Time: SCLK to DIN tHdDi 100 ns Minimum High Time: SCLK tMnHCk 100 ns Minimum Low Time: SCLK tMnLCk 100 ns Minimum Low Time: UPDATE tMnLUd 100 ns Setup Time: UPDATE to SCLK tSuHUd Rising edge of UPDATE to falling edge of SCLK 100 ns Hold Time: SCLK to UPDATE tHdHUd Falling edge of SCLK to falling edge of UPDATE 100 ns Setup Time: MODE to SCLK tSuMd Minimum time from clock edge to MODE with valid data clocking 100 ns Hold Time: MODE to SCLK tHdMd Minimum time from clock edge to MODE with valid data clocking 100 ns Minimum Low Time: RESET tMnLRst 300 ns Delay: RESET tPdRst 10k Ω pulldown to AGND 600 ns |
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