IDT8P34S1212NLI REVISION A JANUARY 20, 2014

2

©2014 Integrated Device Technology, Inc.

IDT8P34S1212I Data Sheet

1:12 LVDS Output 1.8V Fanout Buffer

Pin Descriptions and Characteristics

1.

Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.

Number

Name

Type

Description

1

SEL

Input

Pulldown

Reference select control. See Table 3 for function.

LVCMOS/LVTTL interface levels.

2

CLK1

Input

Pulldown

Non-inverting differential clock/data input.

3

nCLK1

Input

Pulldown/

Pullup

Inverting differential clock input.

4, 10

nc

Unused

Do not connect.

5, 6, 11, 20,

31, 40

Power

Power supply pins.

Bias voltage reference. Provides an input bias voltage for the CLKx, nCLKx

input pairs in AC-coupled applications. Refer to Figures 2B and 2C for

applicable AC-coupled input interfaces.

8

nCLK0

Input

Pulldown/

Pullup

Inverting LVPECL differential clock input.

9

CLK0

Input

Pulldown

Non-inverting LVPECL differential clock/data input.

12, 13

Q0, nQ0

Output

Differential output pair 0. LVDS interface levels.

14, 15

Q1, nQ1

Output

Differential output pair 1. LVDS interface levels.

16, 17

Q2, nQ2

Output

Differential output pair 2. LVDS interface levels.

18, 19

Q3, nQ3

Output

Differential output pair 3. LVDS interface levels.

21, 30

GND

Power

Power supply ground.

22, 23

Q4, nQ4

Output

Differential output pair 4. LVDS interface levels.

24, 25

Q5, nQ5

Output

Differential output pair 5. LVDS interface levels.

26, 27

Q6, nQ6

Output

Differential output pair 6. LVDS interface levels.

28, 29

Q7, nQ7

Output

Differential output pair 7. LVDS interface levels.

32, 33

Q8, nQ8

Output

Differential output pair 8. LVDS interface levels.

34, 35

Q9, nQ9

Output

Differential output pair 9. LVDS interface levels.

36, 37

Q10, nQ10

Output

Differential output pair 10. LVDS interface levels.

38, 39

Q11, nQ11

Output

Differential output pair 11. LVDS interface levels.

Table 2. Pin Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

2

pF

Input Pulldown Resistor

51

k



Input Pullup Resistor

51

k



1.

SEL is an asynchronous control.

Input

Operation

SEL

0 (Default)

CLK0, nCLK0 is the selected differential clock input.

1

CLK1, nCLK1 is the selected differential clock input.