Low-Voltage, Dual-Supply,

SPDT Analog Switch with Enable

tr < 5ns

tf < 5ns

50%

LOGIC

INPUT

COM

GND

IN

0

NO

OR NC

0.9

0.9

SWITCH

OUTPUT

LOGIC

INPUT

LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES

THAT HAVE THE OPPOSITE LOGIC SENSE.

V+

35pF

V+

MAX4564

V-

Figure 2. Switching Time

50%

LOGIC

INPUT

0.9

LOGIC

INPUT

GND

NO

IN

NC

V+

V+

35pF

COM

MAX4564

V-

Figure 3. Break-Before-Make Interval

GND

COM

V+

IN

OFF

ON

OFF

Q = (

NC

OR NO

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

OFF

ON

OFF

IN

V+

V-

IN

MAX4564

Figure 4. Charge Injection

Test Circuits/Timing Diagrams (continued)

_______________________________________________________________________________________

9