8 x 8 Video Crosspoint Switch

4

_______________________________________________________________________________________

______________________________________________________________Pin Description

Note 1: Buffer inputs are internally grounded with a 1000 or 1001 command from the D3-D0 lines. AGND must be at 0.0V since the

gain setting resistors of the buffers are internally tied to AGND.

PIN

NAME

FUNCTION

—

1, 12, 23, 34

N.C.

No connect. Not internally connected.

1

2

D1/SER OUT

Parallel Data Bit D1 when SER/P

—

A

—

R

–

= 0V. Serial Output for cascading

multiple parts when SER/P

—

A

—

R

–

= 5V.

2

3

D0/SER IN

Parallel Data Bit D0 when SER/P

—

A

—

R

–

= 0V. A Serial Input when

SER/P

—

A

—

R

–

= 5V.

3, 4, 6

4, 5, 7

A2, A1, A0

Output Buffer Address Lines

5, 7, 9, 11,

13, 15, 17, 19

6, 8, 10, 13,

15, 17, 19, 21

IN0–IN7

Video lnput Lines

8

9

LOAD

Asynchronous control line. When LOAD = 1, all the 400

Ω internal active

loads are on. When LOAD = 0, external 400

Ω loads must be used. The

buffers MUST have a resistive load to maintain stability.

10, 12

11, 14

DGND

Digital Ground Pins. Both DGND pins must have the same potential and

be bypassed to AGND. DGND should be within ±0.3V of AGND.

14

16

EDGE/

–

L

—

E

—

V

—

E

—

L

–

When this control line is high, the 2nd-rank registers are loaded with the

rising edge of the LATCH line. If this control line is low, the 2nd-rank reg-

isters are transparant when LATCH is low, passing data directly from the

1st-rank registers to the decoders.

16, 26, 40

18, 29, 44

V+

All V+ pins must be tied to each other and bypassed to AGND

separately (Figure 2).

18

20

SER/P

—

A

—

R

–

5V = 32-Bit Serial, 0V = 7-Bit Parallel

20, 34

22, 38

V-

Both V- pins must be tied to each other and bypassed to AGND

separately (Figure 2).

21

24

WR

WRITE in the serial mode, shifts data in. In the parallel mode, WR loads

data into the 1st-rank registers. Data is latched on the rising edge.

22

25

LATCH

If EDGE/

–

L

—

E

—

V

—

E

—

L

–

= 5V, data is loaded from the 1st-rank registers to the 2nd-

rank registers on the rising edge of LATCH. If EDGE/

–

L

—

E

—

V

—

E

—

L

–

= 0V, data is

loaded while LATCH = 0V. In addition, data is loaded during the execution

of parallel-mode functions 1011 through 1110, or if LATCH = 5V during the

execution of the parallel-mode "software-LATCH" command (1111).

23

26

C

—

E

–

–

C

—

h

—

i

—

p

—

—

E

—

n

—

a

—

b

—

l

—

e

–

. When

–

C

—

E

–

= 0V and CE = 5V, the WR line is enabled.

24

27

CE

Chip Enable. When

–

C

—

E

–

= 0V and CE = 5V, the WR line is enabled.

25, 27, 29, 31,

33, 35, 37, 39

28, 30, 32, 35,

37, 39, 41, 43

OUT7-OUT0

Output Buffers 7-0 (Note 1)

28, 30, 32

31, 33, 36

AGND

Analog Ground must be at 0.0V since the gain resistors of the buffers are

tied to these 3 pins.

36

40

D3

Parallel Data Bit D3 when SER/

–

P

—

A

—

R

–

= 0V. When D3 = 0V, D0-D2 specifies

the input channel to be connected to buffer. When D3 = 5V, then D0-D2

specify control codes. D3 is not used when SER/

–

P

—

A

—

R

–

= 5V.

38

42

D2

Parallel Data Bit D2 when SER/

–

P

—

A

—

R

–

= 0V. Not used when

SER/

–

P

—

A

—

R

–

= 5V.

DIP

PLCC