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MAX495CPA Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX495CPA Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 16 page Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op Amps the op amp in an inverting configuration (Figure 3a); connect resistor R3 between the noninverting input and the input signal when using the op amp in a noninvert- ing configuration (Figure 3b). Select R3 to equal the parallel combination of R1 and R2. High source resis- tances will degrade noise performance, due to the ther- mal noise of the resistor and the input current noise (which is multiplied by the source resistance). Input Stage Protection Circuitry The MAX492/MAX494/MAX495 include internal protec- tion circuitry that prevents damage to the precision input stage from large differential input voltages. This protection circuitry consists of back-to-back diodes between IN+ and IN- with two 1.7k Ω resistors in series (Figure 4). The diodes limit the differential voltage applied to the amplifiers’ internal circuitry to no more than VF, where VF is the diodes’ forward-voltage drop (about 0.7V at +25°C). Input bias current for the ICs (±25nA typical) is speci- fied for the small differential input voltages. For large differential input voltages (exceeding VF), this protec- tion circuitry increases the input current at IN+ and IN-: (VIN+ - VIN- ) - VF Input Current = ——————————— 2 x 1.7k Ω For comparator applications requiring large differential voltages (greater than VF), you can limit the input cur- rent that flows through the diodes with external resistors R1 VOUT R3 = R2 II R1 R3 VIN R2 MAX49_ Figure 3a. Reducing Offset Error Due to Bias Current: Inverting Configuration R3 VOUT R3 = R2 II R1 VIN R1 R2 MAX49_ MAX492 MAX494 MAX495 1.7k Ω 1.7k Ω TO INTERNAL CIRCUITRY TO INTERNAL CIRCUITRY IN– IN+ Figure 4. Input Stage Protection Circuitry 10,000 100 1 10 100 RESISTIVE LOAD (k Ω) 1000 UNSTABLE REGION VCC = +5V VOUT = VCC/2 RL TO VEE AV = +1 Figure 5. Capacitive-Load Stable Region Sourcing Current ______________________________________________________________________________________ 11 Figure 3b. Reducing Offset Error Due to Bias Current: Noninverting Configuration |
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