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ICS8745BI-21 Datasheet(PDF) 11 Page - Integrated Device Technology |
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ICS8745BI-21 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 21 page ICS8745BMI-21 REVISION D JULY 28, 2010 11 ©2010 Integrated Device Technology, Inc. ICS8745BI-21 Data Sheet 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver R1 50 Ω R2 50 Ω 1.8V Zo = 50 Ω Zo = 50 Ω CLK nCLK 3.3V LVHSTL IDT LVHSTL Driver Differential Input R3 125 Ω R4 125 Ω R1 84 Ω R2 84 Ω 3.3V Zo = 50 Ω Zo = 50 Ω CLK nCLK 3.3V 3.3V LVPECL Differential Input HCSL *R3 33 Ω *R4 33 Ω CLK nCLK 3.3V 3.3V Zo = 50 Ω Zo = 50 Ω Differential Input R1 50 Ω R2 50 Ω *Optional – R3 and R4 can be 0 Ω CLK nCLK Differential Input LVPECL 3.3V Zo = 50 Ω Zo = 50 Ω 3.3V R1 50 Ω R2 50 Ω R2 50 Ω 3.3V R1 100 Ω LVDS CLK nCLK 3.3V Receiver Zo = 50 Ω Zo = 50 Ω CLK nCLK Differential Input SSTL 2.5V Zo = 60 Ω Zo = 60 Ω 2.5V 3.3V R1 120 Ω R2 120 Ω R3 120 Ω R4 120 Ω |
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