MAX517BCSA datasheet(4/16 Pages) MAXIM

Part #	MAX517BCSA

Description	2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

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4 / 16 page

mA

2-Wire Serial 8-Bit DACs with

Rail-to-Rail Outputs

4

_______________________________________________________________________________________

Note 1:

For the MAX518 (full-scale = VDD) the last three codes are excluded from the TUE and DNL specifications, due to the limited

output swing when loaded with 10k

Ω to GND.

Note 2:

Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.

Note 3:

Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.

Note 4:

VREF_ = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the

code of all other DACs to 00 hex.

Note 5:

VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex.

Note 6:

Guaranteed by design.

Note 7:

I

2C compatible mode.

Note 8:

Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

Note 9:

A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to

bridge the undefined region of SCL’s falling edge.

Note 10: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD.

Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

Hold Time, (Repeated) Start Condition

tHD, STA

0.6

µs

Low Period of the SCL Clock

tLOW

1.3

µs

High Period of the SCL Clock

tHIGH

0.6

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Serial Clock Frequency

fSCL

0

400

kHz

Bus Free Time Between a STOP and a

START Condition

tBUF

1.3

µs

CONDITIONS

µs

Setup Time for a Repeated START Condition

tSU, STA

0.6

µs

Data Hold Time

tHD, DAT

0

0.9

µs

Data Setup Time

tSU, DAT

100

(Note 9)

ns

Fall Time of SDA Transmitting (Note 7)

tF

20 + 0.1Cb

250

ns

Setup Time for STOP Condition

tSU, STO

0.6

µs

Capacitive Load for Each Bus Line

Cb

400

ISINK ≤ 6mA (Note 10)

pF

Rise Time of Both SDA and SCL Signals, Receiving

tR

20 + 0.1Cb

300

ns

Fall Time of Both SDA and SCL Signals, Receiving

tF

20 + 0.1Cb

300

(Note 10)

ns

Pulse Width of Spike Suppressed

tSP

050

(Notes 6, 11)

ns

TIMING CHARACTERISTICS

(VDD = 5V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.)

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted.

Typical values are TA = +25°C.)

PARAMETER

SYMBOL

MIN

TYP

MAX UNITS

CONDITIONS

Digital-Analog Glitch Impulse

12

Code 128 to 127

nV-s

Signal to Noise + Distortion

Ratio (MAX517, MAX519)

SINAD

87

VREF_ = 4Vp-p at 1kHz, VDD = 5V,

Code = FF hex

dB

Multiplying Bandwidth

(MAX517, MAX519)

1

MHz

Wideband Amplifier Noise

60

µVRMS

Supply Voltage

VDD

4.5

5.5

V

1.5

3.0

MAX517E/M

MAX517C

2.5

5

1.5

3.5

VREF_ = 4Vp-p, 3dB bandwidth

Supply Current

Normal mode, output(s)

unloaded, all digital inputs

at 0V or VDD

2.5

6

MAX518C, MAX519C

MAX518E/M, MAX519E/M

IDD

Power-down mode

420

µA

POWER REQUIREMENTS

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