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8T49N242 Datasheet(PDF) 11 Page - Integrated Device Technology

Part # 8T49N242
Description  Auto and manual clock selection with hitless switching
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

8T49N242 Datasheet(HTML) 11 Page - Integrated Device Technology

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REVISION 2 08/07/15
11
FEMTOCLOCK®NG UNIVERSAL FREQUENCY TRANSLATOR
8T49N242 DATA SHEET
I2C Mode Operation
The I2C interface is designed to fully support v1.2 of the I2C
Specification for Normal and Fast mode operation. The device acts
as a slave device on the I2C bus at 100kHz or 400kHz using the
address defined in the Serial Interface Control register (0006h), as
modified by the S_A0 & S_A1 input pin settings. The interface
accepts byte-oriented block write and block read operations. Two
address bytes specify the register address of the byte position of the
first register to write or read. Data bytes (registers) are accessed in
sequential order from the lowest to the highest byte (most significant
bit first). Read and write block transfers can be stopped after any
complete byte transfer. During a write operation, data will not be
moved into the registers until the STOP bit is received, at which point,
all data received in the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 51k
 typical.
Figure 5. I2C Slave Read and Write Cycle Sequencing
I2C Master Mode
When operating in I2C mode, the 8T49N242 has the capability to
become a bus master on the I2C bus for the purposes of reading its
configuration from an external I2C EEPROM. Only a block read cycle
will be supported.
As an I2C bus master, the 8T49N242 will support the following
functions:
• 7-bit addressing mode
• Base address register for EEPROM
• Validation of the read block via CCITT-8 CRC check against value
stored in last byte (84h) of EEPROM
• Support for 100kHz and 400kHz operation with speed negotiation.
If bit d0 is set at Byte address 05h in the EEPROM, this will shift
from 100kHz operation to 400kHz operation.
• Support for 1- or 2-byte addressing mode
• Master arbitration with programmable number of retries
• Fixed-period cycle response timer to prevent permanently hanging
the I2C bus.
• Read will abort with an alarm (BOOTFAIL) if any of the following
conditions occur: Slave NACK, Arbitration Fail, Collision during
Address Phase, CRC failure, Slave Response time-out
The 8T49N242 will not support the following functions:
•I2C General Call
• Slave clock stretching
•I2C Start Byte protocol
• EEPROM Chaining
• CBUS compatibility
• Responding to its own slave address when acting as a master
• Writing to external I2C devices including the external EEPROM
used for booting
Current Read
S
Dev Addr + R
A
Data 0
A
Data 1
A
A
Data n
Ā
P
Sequential Read
S
Dev Addr + W
A
Data 0
A
Data 1
A
A
Data n
Ā
P
Offset Addr MSB
A
Sr
Dev Addr + R
A
Sequential Write
S
Dev Addr + W
A
Data 0
P
A
Data 1
A
A
Data n
A
from master to slave
from slave to master
Offset Addr LSB
A
Offset Addr MSB
A
Offset Addr LSB
A
S= start
Sr = repeated start
A=acknowledge
A=non‐acknowledge
P=stop


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