IDT8N3D085 Data Sheet

LVPECL DUAL FREQUENCY PROGRAMMBLE CRYSTAL OSCILLATOR

IDT8N3D085CCD

REVISION A DECEMBER 14, 2012

10

©2012 Integrated Device Technology, Inc.

Parameter Measurement Information, continued

Output Duty Cycle/Pulse Width/Period

Applications Information

Recommendations for Unused Input Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k

 resistor can be used.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50



transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 1A and 1B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 1A. 3.3V LVPECL Output Termination

Figure 1B. 3.3V LVPECL Output Termination

t

PW

t

PERIOD

t

PW

t

PERIOD

odc =

x 100%

nQ

Q

3.3V

V

R1

50

Ω

R2

50

Ω

RTT

Z

Z

+

_

RTT =

* Z

o

1

((V

3.3V

LVPECL

Input

R1

84

Ω

R2

84

Ω

3.3V

R3

125

Ω

R4

125

Ω

Z

Z

LVPECL

Input

3.3V

3.3V

+

_