IDT8N4S270 Data Sheet

LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR

IDT8N4S270CCD REVISION A AUGUST 31, 2012

7

©2012 Integrated Device Technology, Inc.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.

NOTE 1: This parameter is defined in accordance with JEDEC standard 65.

NOTE 2: Please refer to the phase noise plot.

NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the

optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes.



Single-side band phase noise,



10MHz from Carrier

231.25MHz

-141

dBc/Hz

Output Rise/Fall Time

20% to 80%

50

450

ps

odc

Output Duty Cycle

47

53

%

Device Startup Time After

Power Up

20

ms

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units