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NEURON5000 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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NEURON5000 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 8 page  www.echelon.com ® SCK MOSI MISO CS0~ SDA_CS1~ SCL I2C Slave (EEPROM) SPI Slave (Flash) Series 5000 Chip 3.3 V Figure 4: Using both I2C and SPI Interfaces for External NVM Memories Memory devices supported. The Neuron 5000 Processor supports any EEPROM device that uses the SPI or I2C protocol, and meets the clock speed and addressing requirements described above. While all EEPROM devices have a uniform write procedure, flash devices from various manufacturers differ slightly in their write procedure. Thus, a small library routine is stored in the external EEPROM device that helps the system write successfully to the external flash device. Echelon has qualified the following SPI flash memory devices for use with the Neuron 5000 Processor: • Atmel®AT25F512B512-Kilobit 2.7-voltMinimumSPISerialFlash Memory. • Numonyx™M25P05-A512-Kbit, serialflashmemory,50MHzSPIbus interface. • SiliconStorageTechnology SST25VF512A512KbitSPISerial Flash. • Additionaldevicesmaybequalified inthefuture. Memory map. A Neuron 5000 Processor has a memory map of 64KB. A Neuron C application program uses this memory map to organize its memory and data access. The memory map is a logical view of device memory, rather than a physical view, because the chip’s processors only directly access RAM. The memory map divides the Neuron 5000 Processor’s physical 64KB RAM into the following types of logical memory, as shown in Figure 5: • Systemfirmwareimage(storedin on-chipROMorexternalNVM). • On-chipRAMorNVM.Memory rangesforeachareconfigurable withinthedevicehardware template.Thenon-volatilememory representstheareashadowedfrom externalNVMintotheRAM. • On-chipRAMforstacksegments andRAMNEARdata. • MandatoryexternalEEPROMthat holdsconfigurationdataandnon- volatile applicationvariables. • Reservedspaceforsystemuse. If a 64KB external serial EEPROM or flash device is used, the maximum allowed size of application code is 42KB as defined by extended NVM area in the memory map. An additional 16KB of the remaining space can hold an external system firmware image, in case a future firmware upgrade is required. Reserved Mandatory EEPROM On-Chip RAM Extended Memory (Configurable as: Extended RAM or Non-volatile memory) On-Chip ROM 0x0000 to 0x3FFF 0x4000 to 0xE7FF 0xE800 to 0xEFFF 0xF000 to 0xF7FF 0xF800 to 0xFFFF 2 KB 2 KB 2 KB 42 KB 16 KB Figure 5: FT 5000 Smart Transceiver Memory Map Programming memory devices. Because the Neuron 5000 Processor does not have any on-chip user-accessible NVM, only the external serial EEPROM or flash devices need to be programmed with the application and configuration data. The memory devices can be programmed in any of the following ways: In-circuit programming on the board. Over the network. Pre-programming before soldering on the board. Migration Considerations Most device designs that use the previous- generation Neuron 3120 or Neuron 3150 Chip can transition to using the Neuron 5000 Processor. However, because the supply voltage and memory architecture of Neuron 3120/3150 Chips and Neuron 5000 Processors are different, the transition requires a hardware redesign of the boards. The recommended migration path for devices based on a Neuron Chip depends on the transceiver type used with the Neuron Chip, as shown in Table 2. Current Transceiver Type Used Equivalent Series 5000 Design Comments FTT-10A Transceiver FT 5000 Smart Transceiver plus FT-X3 Communications Transformer Use an FT 5000 Smart Transceiver for TP/FT-10 channels. EIA-485 Transceiver Neuron 5000 Processor plus EIA-485 Transceiver or (if possible) FT 5000 Smart Transceiver plus FT-X3 Communications Transformer If your design is flexible enough to allow either an EIA-485 channel or a TP/FT-10 channel, use the FT 5000 Smart Transceiver with the TP/FT-10 channel. TPT Twisted Pair Transceiver Module (for a TP/XF-1250 channel type) Neuron 5000 Processor plus TPT/XF-1250 Twisted Pair Transceiver Module (for a TP/XF-1250 channel type) The Neuron 5000 Processor must be configured to operate in 3.3V Single-Ended Mode with the TPT Twisted Pair Transceiver Module and external circuitry must be added for Single-Ended to Differential Mode conversion. LonWorks LPT-11 Link Power Transceiver Neuron 5000 Processor plus LPT-11 Link Power Transceiver The Neuron 5000 Processor must be configured to operate in 3.3V Single-Ended Mode with the LPT-11 Link Power Transceiver. Other transceiver type Neuron 5000 Processor plus other transceiver type The Neuron 5000 Processor can connect to other transceiver types for the supported channel types, but more hardware design work may be required. Table 2: Migration for Devices with Neuron Chips See the Series 5000 Chip Data Book and the Connecting a Neuron 5000 Processor to an External Transceiver Engineering Bulletin for more information about migrating device designs for Neuron 3120/3150 Chips to Neuron 5000 Processors. |
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