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CC430F5143 Datasheet(PDF) 7 Page - Texas Instruments |
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CC430F5143 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 118 page RGZ PACKAGE (TOP VIEW) 12 11 4 3 2 1 10 9 8 7 6 5 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 P1.1/PM_RFGDO2 P1.2/PM_UCB0SOMI/PM_UCB0SCL P1.7/PM_UCA0CLK/PM_UCB0STE P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 P2.1/PM_TA1CCR0A/CB1/A1 P2.2/PM_TA1CCR1A/CB2/A2 P1.3/PM_UCB0SIMO/PM_UCB0SDA P1.4/PM_UCB0CLK/PM_UCA0STE DVCC VCORE P1.5/PM_UCA0RXD/PM_UCA0SOMI P1.6/PM_UCA0TXD/PM_UCA0SIMO RF_XIN RF_XOUT AVCC_RF GUARD PJ.0/TDO PJ.1/TDI/TCLK AVCC_RF RF_P RF_N AVCC_RF AVCC_RF R_BIAS VSS Exposed die attached pad CC430F514x ECCN 5E002 TSPA - Technology / Software Publicly Available CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013 NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. Pinout shows only the default mapping. See Table 10 for details. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 |
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