Electronic Components Datasheet Search |
|
MAX533AMJE Datasheet(PDF) 4 Page - Maxim Integrated Products |
|
MAX533AMJE Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 16 page 2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers 4 _______________________________________________________________________________________ TIMING CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) Note 1: INL and DNL are measured with RL referenced to ground. Nonlinearity is measured from the first code that is greater than or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offset section. Note 2: VREF = 2.5Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all other DAC’s codes to 00 hex. Note 3: VREF = 2.5Vp-p, 10kHz. DAC code = 00 hex. Note 4: Guaranteed by design, not production tested. Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of VOUT’s final value. Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC. Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for tLDAC or longer after CS goes high. Note 8: When DOUT is not used. If DOUT is used, fCLK max is 4MHz, due to the SCLK to DOUT propagation delay. Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD). Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD). CS Rise to SCLK Rise Setup Time tCS1 50 ns SCLK Rise to CS Fall Delay tCS0 50 ns MAX533M MAX533M 40 40 MAX533C/E MAX533C/E SCLK Fall to DOUT Valid Propagation Delay (Note 10) tDO2 250 ns MAX533M 210 MAX533C/E SCLK Rise to DOUT Valid Propagation Delay (Note 9) tDO1 230 ns MAX533M 200 MAX533C/E 40 CS Fall to SCLK Rise Setup Time tCSS 50 40 ns SCLK Pulse Width Low tCL 50 ns MAX533C/E MAX533M MAX533C/E MAX533M 40 SCLK Pulse Width High tCH 50 ns MAX533C/E MAX533M PARAMETER SYMBOL MIN TYP MAX UNITS SERIAL-INTERFACE TIMING 10 SCLK Clock Frequency (Note 8) fCLK 8.3 MHz SCLK Rise to CS Rise Hold Time tCSH 0 ns 40 DIN to SCLK Rise to Setup Time tDS 50 DIN to SCLK Rise to Hold Time tDH 0 ns CONDITIONS MAX533C/E MAX533M MAX533C/E MAX533M |
Similar Part No. - MAX533AMJE |
|
Similar Description - MAX533AMJE |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |