Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

4

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ELECTRICAL CHARACTERISTICS—MAX536 (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

20

µs

SCK Clock Period

100

ns

SCK Pulse Width High

30

ns

SCK Pulse Width Low

30

ns

20

ns

10

ns

SDI Setup Time

40

26

ns

SDI Hold Time

0

ns

1k

Ω pull-up on SDO

SDO high

78

105

ns

SDO low

50

80

SCK Fall to SDO Valid

Propagation Delay (Note 7)

1k

Ω pull-up on SDO

SDO high

81

110

ns

SDO low

53

85

27

45

ns

40

60

ns

SCK Rise to CS Fall Delay

Continuous SCK, SCK edge ignored

20

ns

SCK edge ignored

20

ns

LDAC Pulse Width Low

30

ns

CS Pulse Width High

40

ns

Internal Power-On Reset

Pulse Width (Note 2)

CS Fall to SCK Rise

Setup Time

SCK Rise to CS Rise

Hold Time

SCK Rise to SDO Valid

Propagation Delay (Note 6)

CS Fall to SDO Enable

(Note 8)

CS Rise to SDO Disable

(Note 9)

CS Rise to SCK Rise

Hold Time

Note 1: TUE is specified with no resistive load.

Note 2: Guaranteed by design.

Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.

≤ 5ns. Logic input swing is 0V to 5V.

Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO

pin has an internal active pull-up.)

Note 7: Serial data clocked out of SDO on SCK’s rising edge.

Note 8: SDO changes from High-Z state to 90% of final value.

Note 9: SDO rises 10% toward High-Z state.

TIMING CHARACTERISTICS (Note 5)