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MAX531AEPD Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX531AEPD Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 16 page Daisy-Chaining Devices The serial output, DOUT, allows cascading of two or more DACs. The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. For low power, DOUT is a CMOS output that does not require an external pull-up resistor. DOUT does not go into a high-impedance state when CS is high. DOUT changes on SCLK’s falling edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. Any number of MAX531/MAX538/MAX539 DACs can be daisy-chained by connecting the DOUT of one device to the DIN of the next device in the chain. For proper timing, ensure that tCL (CS low to SCLK high) is greater than tDO + tDS. Unipolar Configuration The MAX531 is configured for a gain of +1 (0V to VREFIN unipolar output) by connecting BIPOFF and RFB to VOUT (Figure 6). The converter operates from either sin- gle or dual supplies in this configuration. See Table 1 for the DAC-latch contents (input) vs. the analog VOUT (output). In this range, 1LSB = VREFIN (2-12). The MAX538 is internally configured for unipolar gain = +1 operation. A gain of +2 (0V to 2VREFIN unipolar output) is set up by connecting BIPOFF to AGND and RFB to VOUT (Figure 7). Table 2 shows the DAC-latch contents vs. VOUT. The MAX531 operates from either single or dual supplies in this mode. In this range, 1LSB = (2)(VREFIN) (2-12) = (VREFIN)(2-11). The MAX539 is internally config- ured for unipolar gain = +2 operation. Bipolar Configuration A bipolar range is set up by connecting BIPOFF to REFIN and RFB to VOUT, and operating from dual (±5V) supplies (Figure 8). Table 3 shows the DAC-latch contents (input) vs. VOUT (output). In this range, 1LSB = VREFIN (2-11). Four-Quadrant Multiplication The MAX531 can be used as a four-quadrant multiplier by connecting BIPOFF to REFIN and RFB to VOUT, using (1) an offset binary digital code, (2) bipolar power supplies, using dual power supplies, and (3) a bipolar analog input at REFIN within the range VSS + 2V to VDD - 2V, as shown in Figure 9. In general, a 12-bit DAC’s output is (D) (VREFIN) (G), where “G” is the gain (+1 or +2) and “D” is the binary representation of the digital input divided by 212 or 4096. This formula is precise for unipolar operation. However, for bipolar, offset binary operation, the MSB is really a polarity bit. No resolution is lost, as there are the same number of steps. The output voltage, howev- er, has been shifted from a range of, for example, 0V to 4.096V (G = +2) to a range of -2.048V to +2.048V. Keep in mind that when using the DAC as a four-quad- rant multiplier, the scale is skewed. Negative full scale is -VREFIN, while positive full scale is +VREFIN - 1LSB. +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs 10 ______________________________________________________________________________________ MAX531 CONNECT BIPOFF TO VOUT FOR G = 1, TO AGND FOR G = 2, OR TO REFIN FOR BIPOLAR GAIN INVERTED R-2R DAC DIN DOUT SCLK CS CLR 2.048V REFIN REFOUT AGND DGND VDD VSS +5V 0V TO -5V 33 µF 0.1 µF 0.1 µF 2R 2R BIPOFF RFB VOUT MAX538 MAX539 INVERTED R-2R DAC DIN DOUT SCLK CS REFIN AGND +5V VDD VOUT MAX539 ONLY 0.1 µF 2R 2R Figure 3a. MAX531 Typical Operating Circuit Figure 3b. MAX538/MAX539 Typical Operating Circuit |
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