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RF430FRL154H Datasheet(PDF) 7 Page - Texas Instruments |
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RF430FRL154H Datasheet(HTML) 7 Page - Texas Instruments |
7 / 51 page RF430FRL152H, RF430FRL153H, RF430FRL154H www.ti.com SLAS834C – NOVEMBER 2012 – REVISED DECEMBER 2014 4.2 Signal Descriptions Table 4-1 describes the signals. Table 4-1. Signal Descriptions TERMINAL I/O(1) DESCRIPTION NAME NO. ANT1 1 I Antenna input 1 ANT2 2 I Antenna input 2 VDDSW 3 Switched supply voltage VDDB 4 Battery supply voltage CP1 5 Charge pump flying cap terminal 1 CP2 6 Charge pump flying cap terminal 2 VDD2X 7 Voltage doubler output P1.3 General-purpose digital I/O SPI_STE SPI slave transmit enable 8 I/O TA0.2 Timer_A TA0 OUT2 output ACLK ACLK output (divided by 1, 2, 4, 8, 16, or 32) TA0CLK Timer_A TA0 clock signal TA0CLK input P1.2 General-purpose digital I/O SPI_CLK SPI clock 9 I/O MCLK MCLK output TA0.0 Timer_A TA0 OUT0 output Reset input active low RST/NMI 10 I Non-maskable interrupt input P1.1 General-purpose digital I/O SPI_SOMI SPI slave out master in SCL I2C clock 11 I/O ACLK ACLK output (divided by 1, 2, 4, or 8 ) TA0.2 Timer_A TA0 OUT2 output CCI0.0 Timer_A TA0 CCR0 capture: CCI0B input, compare P1.0 General-purpose digital I/O SPI_SIMO SPI slave in master out SDA I2C data 12 I/O SMCLK SMCLK output TA0.1 Timer0_A3 OUT1 output CCI0.0 Timer_A TA0 CCR0 capture: CCI0A input, compare ADC0 13 I ADC input pin 0 TST2 14 Internal; connect to GND SVSS 15 Sensor reference potential TST1 16 Internal; connect to GND ADC1 / TEMP1 17 ADC input pin 1 / Resistive bias pin 1 ADC2 / TEMP2 18 ADC input pin 2 / Resistive bias pin 2 (1) I = input, O = output Copyright © 2012–2014, Texas Instruments Incorporated Terminal Configuration and Functions 7 Submit Documentation Feedback Product Folder Links: RF430FRL152H RF430FRL153H RF430FRL154H |
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