6 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB

2

REVISION C 04/22/15

9DBU0631 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

PLL Operating Mode

40 39 38 37 36 35 34 33 32 31

vSADR_tri 130 NC

^vHIBW_BYPM_LOBW# 229 vOE3#

FB_DNC 328 DIF3#

FB_DNC# 427 DIF3

VDDR1.5 526 VDDIO

CLK_IN 625 VDDA1.5

CLK_IN# 724 vOE2#

GNDDIG 823 DIF2#

SCLK_3.3 922 DIF2

SDATA_3.3 10

21 vOE1#

11 12 13 14 15 16 17 18 19 20

40-VFQFPN, 5mm x 5mm 0.4mm pin pitch

^ prefix indicates internal 120KOhm pull up resistor

^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)

v prefix indicates internal 120KOhm pull down resistor

9DBU0631

epad is GND

SADR

Address

0

1101011

M

1101100

1

1101101

x

State of SADR on first application of

CKPWRGD_PD#

+

Read/Write bit

x

x

True O/P Comp. O/P

0

X

X

X

Low

Low

Off

1

Running

0

X

Low

Low

On

1

1

Running

1

0

Running

Running

On

1

1

Running

1

1

Low

Low

On

1

PLL

CKPWRGD_PD#

SMBus

OEx bit

1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table.

CLK_IN

DIFx

OEx# Pin

Pin Number

VDD

VDDIO

GND

541

Input

receiver

analog

11

8

Digital Power

16,31

12,17,26,32,39

41

DIF outputs,

Logic

25

41

PLL Analog

Description

HiBW_BypM_LoBW#

MODE

Byte1 [7:6]

Readback

Byte1 [4:3]

Control

0

PLL Lo BW

00

00

MBypass

01

01

1

PLL Hi BW

11

11