Ultra-Low-Power, High-Dynamic

Performance, 7.5Msps Analog Front End

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5

ELECTRICAL CHARACTERISTICS (continued)

°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DAC ANALOG OUTPUT

Full-Scale Output Voltage

±400

mV

Output Common-Mode Range

1. 29

1. 5

V

ADC-DAC INTERCHANNEL CHARACTERISTICS

ADC-DAC Isolation

75

dB

ADC-DAC TIMING CHARACTERISTICS

CLK Rise to I-ADC Channel-I

Output Data Valid

Figure 3 (Note 4)

7.4

9

ns

CLK Fall to Q-ADC Channel-Q

Output Data Valid

Figure 3 (Note 4)

6.9

9

ns

I-DAC Data to CLK Fall Setup

Time

Figure 4 (Note 4)

10

ns

Q-DAC Data to CLK Rise Setup

Time

Figure 4 (Note 4)

10

ns

CLK Fall to I-DAC Data Hold

Time

Figure 4 (Note 4)

0

ns

CLK rise to Q-DAC Data Hold

Time

Figure 4 (Note 4)

0

ns

Clock Duty Cycle

50

%

CLK Duty-Cycle Variation

±15

%

Digital Output Rise/Fall Time

20% to 80%

2.6

ns

SERIAL INTERFACE TIMING CHARACTERISTICS

Falling Edge of CS to Rising

Edge of First SCLK Time

Figure 5 (Note 4)

10

ns

DIN to SCLK Setup Time

Figure 5 (Note 4)

10

ns

DIN to SCLK Hold Time

Figure 5 (Note 4)

0

ns

SCLK Pulse Width High

Figure 5 (Note 4)

25

ns

SCLK Pulse Width Low

Figure 5 (Note 4)

25

ns

SCLK Period

Figure 5 (Note 4)

50

ns

SCLK to CS Setup Time

Figure 5 (Note 4)

0

ns

CS High Pulse Width

Figure 5 (Note 4)

80

ns

MODE RECOVERY TIMING CHARACTERISTICS

From shutdown to Rx mode, Figure 6, ADC

settles to within 1dB

20

Shutdown Wake-Up Time

From shutdown to Tx mode, Figure 6, DAC

settles to within 10 LSB error.

40

µs