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9DBV0431 Datasheet(PDF) 8 Page - Integrated Device Technology

Part # 9DBV0431
Description  HCSL compatible differential input
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9DBV0431 Datasheet(HTML) 8 Page - Integrated Device Technology

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4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB
8
REVISION C 11/26/14
9DBV0431 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Scope averaging on 3.0V/ns setting
2
3.2
4
V/ns
1, 2, 3
Scope averaging on 2.0V/ns setting
1.3
2.3
3.3
V/ns
1, 2, 3
Slew rate matching
ΔTrf
Slew rate matching, Scope averaging on
5.4
20
%
1, 2, 4
Voltage High
VHIGH
660
779
850
1,7
Voltage Low
VLOW
-150
21
150
1,7
Max Voltage
Vmax
835
1150
1
Min Voltage
Vmin
-300
-42
1
Vswing
Vswing
Scope averaging off
300
1515
mV
1,2,7
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
409
550
mV
1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
14
140
mV
1, 6
2 Measured from differential waveform
Slew rate
Trf
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
7 At default SMBus settings.
1Guaranteed by design and characterization, not 100% tested in production. C
L = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential
trace impedance).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
IDDROP
VDDR, @100MHz
4.2
6
mA
1
IDDOP
VDDA + VDD1.8, @100MHz
27
33
mA
1
IDDROP
VDDR, @100MHz
2.2
3
mA
1
IDDOP
VDDA + VDD1.8, @100MHz
20
25
mA
1
IDDRPD
VDDR, CKPWRGD_PD# = 0
0.014
0.3
mA
1,2
IDDPD
VDDA + VDD1.8, CKPWRGD_PD# = 0
0.95
1.2
mA
1, 2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped, and CKPWRGD_PD# pin low.
Operating Supply Current
(PLL Mode)
Operating Supply Current
(PLL-Bypass Mode)
Powerdown Current


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