IRMCF183M

© 2014 International Rectifier

October 2, 2014

List of Figures

Figure 1 Typical Application Block Diagram Using IRMCF183M ................................................ 5

Figure 2 Pinout of IRMCF183M.................................................................................................. 6

Figure 3 Crystal circuit example ................................................................................................16

Figure 4 Voltage droop and S/H hold time.................................................................................17

Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps.........................18

Figure 6 SYNC timing ...............................................................................................................19

Figure 7 Gatekill timing .............................................................................................................20

Figure 8 ITRIP timing ................................................................................................................20

Figure 9 UART timing................................................................................................................21

Figure 10. Interrupt timing .........................................................................................................22

Figure 11 JTAG timing ..............................................................................................................23

Figure 12 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output ................................24

Figure 13 All digital I/O except motor PWM output ....................................................................24

Figure 14 RESET, GATEKILL I/O .............................................................................................25

Figure 15 Analog input ..............................................................................................................25

Figure 16 Analog operational amplifier output and AREF I/O structure .....................................25

Figure 17 VPP programming pin I/O structure...........................................................................26

Figure 18 VSS and AVSS pin structure .....................................................................................26

Figure 19 VDD1 and VDDCAP pin structure .............................................................................26

Figure 20 XTAL0/XTAL1 pins structure .....................................................................................26