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89HPES32NT8BG2 Datasheet(PDF) 6 Page - Integrated Device Technology |
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89HPES32NT8BG2 Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 35 page  IDT 89HPES32NT8BG2 Datasheet 6 of 35 December 17, 2013 Signal Type Name/Description GCLKN[1:0] GCLKP[1:0] I Global Reference Clock. Differential reference clock input pairs. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic. The frequency of the differential reference clock is determined by the GCLKFSEL signal. Note: Both pairs of the Global Reference Clocks must be connected to and derived from the same clock source. Refer to the Overview section of Chapter 2 in the PES32NT8xG2 User Manual for additional details. P00CLKN P00CLKP I Port Reference Clock. Differential reference clock pair associated with port 0. P02CLKN P02CLKP I Port Reference Clock. Differential reference clock pair associated with port 2. P04CLKN P04CLKP I Port Reference Clock. Differential reference clock pair associated with port 4. Table 3 Reference Clock Pins Signal Type Name/Description MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. SSMBADDR[2] I Slave SMBus Address. This pin determines the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 4 SMBus Interface Pins |
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