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MAX6316 Datasheet(PDF) 6 Page - Maxim Integrated Products

Part No. MAX6316
Description  5-Pin μP Supervisory Circuits with Watchdog and Manual Reset
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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5-Pin µP Supervisory Circuits with
Watchdog and Manual Reset
6
_______________________________________________________________________________________
_______________Detailed Description
A microprocessor’s (µP) reset input starts or restarts the
µP in a known state. The reset output of the MAX6316–
MAX6322 µP supervisory circuits interfaces with the
reset input of the µP, preventing code-execution errors
during power-up, power-down, and brownout condi-
tions (see the
Typical Operating Circuit). The MAX6316/
MAX6317/MAX6318/MAX6320/MAX6321 are also capa-
ble of asserting a reset should the µP become stuck in
an infinite loop.
Reset Output
The MAX6316L/MAX6318LH/MAX6319LH feature an
active-low reset output, while the MAX6317H/
MAX6318_H/MAX6319_H/MAX6321HP/MAX6322HP
feature an active-high reset output. RESET is guaran-
teed to be a logic low and RESET is guaranteed to be a
logic high for VCC down to 1V.
The MAX6316–MAX6322 assert reset when VCC is below
the reset threshold (VRST), when MR is pulled low
(MAX6316_/MAX6317H/MAX6319_H/MAX6320P/
MAX6322HP only), or if the WDI pin is not serviced within
the watchdog timeout period (tWD). Reset remains assert-
ed for the specified reset active timeout period (tRP) after
VCC rises above the reset threshold, after MR transitions
low to high, or after the watchdog timer asserts the reset
(MAX6316_/MAX6317H/MAX6318_H/MAX6320P/
MAX6321HP). After the reset active timeout period (tRP)
expires, the reset output deasserts, and the watchdog
timer restarts from zero (Figure 2).
MAX6316–MAX6322
VCC
VCC
WDI
(ALL EXCEPT
MAX6319/MAX6322)
1.23V
52k
52k
GND
RESET
(ALL EXCEPT
MAX6316/MAX6320P)
RESET
(ALL EXCEPT MAX6317)
MR
(ALL EXCEPT
MAX6318/MAX6321)
RESET
GENERATOR
WATCHDOG
TIMER
WATCHDOG
TRANSITION
DETECTOR
Figure 1. Functional Diagram
VCC
1V
1V
tRD
VRST
VRST
tRD
RESET
GND
RESET
tRP
tRP
GND
Figure 2. Reset Timing Diagram




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