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BLM7G1822S-40PB Datasheet(PDF) 11 Page - NXP Semiconductors |
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BLM7G1822S-40PB Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 18 page BLM7G1822S-40PB_S-40PBG All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 3 — 1 July 2015 11 of 18 NXP Semiconductors BLM7G1822S-40PB(G) LDMOS 2-stage power MMIC 8.4 Graphs Tcase = 25 C; VDS =28V; IDq1 =40mA; IDq2 = 120 mA; PL = 4 W. Per section. (1) magnitude of Gp (2) magnitude of RLin Tcase = 25 C; VDS =28V; IDq1 =40mA; IDq2 =120 mA; PL = 4 W. Per section. (1) magnitude of Gp (2) magnitude of RLin Fig 9. Wideband power gain and input return loss as function of frequency; typical values Fig 10. In-band power gain and input return loss as function of frequency; typical values Tcase = 25 C; VDS =28V; IDq1 =40mA; IDq2 = 120 mA. Per section. (1) f = 1805 MHz (2) f = 1960 MHz (3) f = 2170 MHz Tcase = 25 C; VDS =28V; IDq1 =40mA; IDq2 =120 mA. Per section. (1) f = 1805 MHz (2) f = 1960 MHz (3) f = 2170 MHz Fig 11. Power gain and drain efficiency as function of output power; typical values Fig 12. 27 dBm normalized phase response as a function of output power; typical values |
Similar Part No. - BLM7G1822S-40PB_15 |
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Similar Description - BLM7G1822S-40PB_15 |
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