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ICS95V847 Datasheet(PDF) 1 Page - Integrated Device Technology |
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ICS95V847 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 9 page  Integrated Circuit Systems, Inc. ICS95V847 0718E—11/24/08 Block Diagram PLL FB_INT FB_INC CLK_INC CLK_INT FB_OUTT FB_OUTC CLKT0 CLKT1 CLKT2 CLKT3 CLKT4 CLKC0 CLKC1 CLKC2 CLKC3 CLKC4 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) Pin Configuration 24-Pin TSSOP Recommended Application: • Zero Delay Board Fan Out, SO-DIMM • Provides complete DDR registered DIMM solution with ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852 Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 5 differential clock distribution (SSTL_2) • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs Switching Characteristics: • CYCLE - CYCLE jitter: <60ps • OUTPUT - OUTPUT skew: <60ps • Period jitter: ±30ps • DUTY CYCLE: 49.5% - 50.5% Functionality S T U P N IS T U P T U O e t a t S L L P D D V AT N I _ K L CC N I _ K L CT K L CC K L CT T U O _ B FC T U O _ B F D N GL H L H L H f f o / d e s s a p y B D N GH L H L H L f f o / d e s s a p y B V 5 . 2 ) m o n ( LH L H L H n o V 5 . 2 ) m o n ( HL H L H L n o 4.40 mm. Body, 0.65 mm. pitch GND CLKC0 CLKT0 GND VDD CLK_INT CLK_INC AVDD AGND CLKC1 CLKT1 VDD CLKT4 CLKC4 CLKC3 CLKT3 VDD FB_INT FB_INC FB_OUTC FB_OUTT CLKT2 CLKC2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 |
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