VDD

EN

IN

OUT

VDD Threshold

UDG-11228

UCC27528-Q1

www.ti.com

SNVSA89A – DECEMBER 2014 – REVISED MAY 2015

8.3 Feature Description

The UCC27528-Q1 device has internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply-

circuit blocks. When the VDD supply is rising and the level is still below UVLO threshold, the circuit (as shown in

the Functional Block Diagram) holds the output low, regardless of the status of the inputs. The UVLO threshold is

4.25 V (typical) with 350-mV hysteresis (typical). This hysteresis helps prevent chatter when low VDD supply

voltages have noise from the power supply and also when droops in the VDD bias voltage occur when the

voltage levels, such as below 5 V, along with best-in-class switching characteristics, is well suited for driving

emerging GaN-power semiconductor devices.

UVLO threshold is reached. The output is then in-phase with the input.

Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit

performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface-

mount components is highly recommended. A 0.1-

μF ceramic capacitor should be located as close as possible to

the VDD to GND pins of the gate-driver device. In addition, to help deliver the high-current peaks required by the

load, a larger capacitor (such as a 1-

μF capacitor) with relatively low ESR should be connected in parallel and

close proximity. The parallel combination of capacitors should present a low impedance characteristic for the

expected current levels and switching frequencies in the application.

Figure 20. Power-Up Non-Inverting Driver

8.3.2 Operating Supply Current

typical operating supply current in the UVLO state and fully-on state (under static and switching conditions). The

switching, and any current related to pullup resistors on the enable pins and inverting input pins.

device attesting to the high-speed characteristics.

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