SOT23, Low-Power µP Supervisory Circuits

with Battery Backup and Chip-Enable Gating

_______________________________________________________________________________________

7

Pin Description

PIN

NAME

FUNCTION

RESET

MR is low, or RESET IN is low. It asserts in pulses when the internal watchdog times out. RESET remains

input goes from low to high, after RESET IN goes high, or after the watchdog triggers a reset event.

RESET is an open-drain active-high reset output.

1

RESET

rises above the reset threshold, after the manual reset input goes from low to high, after RESET

IN goes high, or after the watchdog triggers a reset event. The MAX636_L is an active-low push-

pull output, while the MAX636_P is an active-low open-drain output.

2

CE IN

Chip-Enable Input. The input to chip-enable gating circuitry. Connect to GND or OUT if not used.

3

GND

Ground

MR

MAX6365 Manual-Reset Input. Maintaining logic low on MR asserts a reset. Reset output

Ω

WDI

MAX6366 Watchdog Input. If WDI remains high or low for longer than the watchdog timeout

a rising or falling edge (Figure 2).

BATT ON

MAX6367 Battery-On Output. BATT ON goes high when in battery backup mode.

4

RESET IN

MAX6368 Reset Input. When RESET IN falls below 1.235V, reset asserts. Reset output remains

6

OUT

is below the reset threshold.

7

BATT

8

CE OUT

Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE

IN is low when reset is asserted, CE OUT will stay low for 12µs (typ) or until CE IN goes high,

whichever occurs first.