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MAX6365PKA31-T Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX6365PKA31-T Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 15 page SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable Gating _______________________________________________________________________________________ 7 Pin Description PIN NAME FUNCTION RESET Active-High Reset Output. RESET asserts high continuously when VCC is below the reset threshold (VTH), MR is low, or RESET IN is low. It asserts in pulses when the internal watchdog times out. RESET remains asserted for the reset timeout period (tRP) after VCC rises above the reset threshold, after the manual reset input goes from low to high, after RESET IN goes high, or after the watchdog triggers a reset event. RESET is an open-drain active-high reset output. 1 RESET Active-Low Reset Output. RESET asserts low continuously when VCC is below the reset threshold (VTH), the manual reset input is low, or RESET IN is low. It asserts low in pulses when the internal watchdog times out. RESET remains asserted low for the reset timeout period (tRP) after VCC rises above the reset threshold, after the manual reset input goes from low to high, after RESET IN goes high, or after the watchdog triggers a reset event. The MAX636_L is an active-low push- pull output, while the MAX636_P is an active-low open-drain output. 2 CE IN Chip-Enable Input. The input to chip-enable gating circuitry. Connect to GND or OUT if not used. 3 GND Ground MR MAX6365 Manual-Reset Input. Maintaining logic low on MR asserts a reset. Reset output remains asserted as long as MR is low and for the reset timeout period (tRP) after MR transitions from low to high. Leave unconnected, or connect to VCC if not used. MR has an internal 20k Ω pullup to VCC. WDI MAX6366 Watchdog Input. If WDI remains high or low for longer than the watchdog timeout period (tWD), the internal watchdog timer runs out and a reset pulse is triggered for the reset timeout period (tRP). The internal watchdog clears whenever reset asserts or whenever WDI sees a rising or falling edge (Figure 2). BATT ON MAX6367 Battery-On Output. BATT ON goes high when in battery backup mode. 4 RESET IN MAX6368 Reset Input. When RESET IN falls below 1.235V, reset asserts. Reset output remains asserted as long as RESET IN is low and for at least tRP after RESET IN goes high. 5VCC Supply Voltage, 1.2V to 5.5V. Reset asserts when VCC drops below the reset threshold voltage (VTH). Reset remains asserted until VCC rises above VTH and for at least tRP after VCC rises above VTH. 6 OUT Output. OUT sources from VCC when not in reset and from the greater of VCC or BATT when VCC is below the reset threshold. 7 BATT Backup-Battery Input. When VCC falls below the reset threshold, OUT switches to BATT if VBATT is 20mV greater than VCC. When VCC rises 20mV above VBATT, OUT switches to VCC. The 40mV hysteresis prevents repeated switching if VCC falls slowly. 8 CE OUT Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE IN is low when reset is asserted, CE OUT will stay low for 12µs (typ) or until CE IN goes high, whichever occurs first. |
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