Electronic Components Datasheet Search |
|
MAX6733UTZGD3-T Datasheet(PDF) 10 Page - Maxim Integrated Products |
|
MAX6733UTZGD3-T Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 16 page The RSTIN comparator derives power from VCC1, and the input voltage must remain less than or equal to VCC1. Low leakage current at RSTIN allows the use of large-valued resistors, resulting in reduced power con- sumption of the system. Watchdog The watchdog feature monitors µP activity through the watchdog input (WDI). A rising or falling edge on WDI within the watchdog timeout period (tWD) indi- cates normal µP operation. WDO asserts low if WDI remains high or low for longer than the watchdog timeout period. Floating WDI does not disable the watchdog timer. The MAX6730–MAX6735 include a dual-mode watch- dog timer to monitor µP activity. The flexible timeout architecture provides a long-period initial watchdog mode, allowing complicated systems to complete lengthy boots, and a short-period normal watchdog mode, allowing the supervisor to provide quick alerts when processor activity fails. After each reset event (VCC power-up, brownout, or manual reset), there is a long initial watchdog period of 35s (min). The long watchdog period mode provides an extended time for the system to power up and fully initialize all µP and system components before assuming responsibility for routine watchdog updates. The usual watchdog timeout period (1.12s min) begins after the initial watchdog timeout period (tWD-L) expires or after the first transition on WDI (Figure 3). During nor- mal operating mode, the supervisor asserts the WDO output if the µP does not update the WDI with a valid transition (high to low or low to high) within the standard timeout period (tWD-S) (1.12s min). Connect MR to WDO to force a system reset in the event that no rising or falling edge is detected at WDI within the watchdog timeout period. WDO asserts low when no edge is detected by WDI, the RST output asserts low, the watchdog counter immediately clears, and WDO returns high. The watchdog counter restarts, using the long watchdog period, when the reset timeout period ends (Figure 4). Ensuring a Valid RESET Output Down to VCC = 0 The MAX6730–MAX6735 guarantee proper operation down to VCC = +0.8V. In applications that require valid reset levels down to VCC = 0, use a 100k Ω pulldown resistor from RST to GND. The resistor value used is not critical, but it must be large enough not to load the reset output when VCC is above the reset threshold. For most applications, 100k Ω is adequate. Note that this configuration does not work for the open-drain outputs of MAX6730/MAX6732/MAX6734. Single-/Dual-/Triple-Voltage µP Supervisory Circuits with Independent Watchdog Output 10 ______________________________________________________________________________________ tRP VTH VCC (MIN) VCC1, VCC2 RSTIN RST WDO WDI <tWD-S <tWD-S >tWD-S tWD-S <tWD-S <tWD-S <tWD-L Figure 3. Watchdog Input/Output Timing Diagram (MR and WDO Not Connected) |
Similar Part No. - MAX6733UTZGD3-T |
|
Similar Description - MAX6733UTZGD3-T |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |