the input voltage must remain less than or equal to

large-valued resistors, resulting in reduced power con-

sumption of the system.

Watchdog

The watchdog feature monitors µP activity through

the watchdog input (WDI). A rising or falling edge on

cates normal µP operation. WDO asserts low if WDI

remains high or low for longer than the watchdog

timeout period. Floating WDI does not disable the

watchdog timer.

The MAX6730–MAX6735 include a dual-mode watch-

dog timer to monitor µP activity. The flexible timeout

architecture provides a long-period initial watchdog

mode, allowing complicated systems to complete

lengthy boots, and a short-period normal watchdog

mode, allowing the supervisor to provide quick alerts

when processor activity fails. After each reset event

long initial watchdog period of 35s (min). The long

watchdog period mode provides an extended time for

the system to power up and fully initialize all µP and

system components before assuming responsibility for

routine watchdog updates.

The usual watchdog timeout period (1.12s min) begins

or after the first transition on WDI (Figure 3). During nor-

mal operating mode, the supervisor asserts the WDO

output if the µP does not update the WDI with a valid

transition (high to low or low to high) within the standard

Connect MR to WDO to force a system reset in the

event that no rising or falling edge is detected at WDI

within the watchdog timeout period. WDO asserts low

when no edge is detected by WDI, the RST output

asserts low, the watchdog counter immediately clears,

and WDO returns high. The watchdog counter restarts,

using the long watchdog period, when the reset timeout

period ends (Figure 4).

Ensuring a Valid RESET

The MAX6730–MAX6735 guarantee proper operation

Ω pulldown

resistor from RST to GND. The resistor value used is not

critical, but it must be large enough not to load the

most applications, 100k

Ω is adequate. Note that this

configuration does not work for the open-drain outputs

of MAX6730/MAX6732/MAX6734.

Single-/Dual-/Triple-Voltage µP Supervisory

Circuits with Independent Watchdog Output

10

______________________________________________________________________________________

(MIN)

RSTIN

RST

WDO

WDI

Figure 3. Watchdog Input/Output Timing Diagram (MR and WDO Not Connected)