OUT 1

OUT2

VCC

IN2

Pre-

drive

VCC

PWM

OCP

OCP

IN1

VSET

Integrator

DIFF

COMP

DCM

/4

ISEN

+

-

COMP

REF

ITRIP

DRV8832-Q1

www.ti.com

SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014

Figure 3. Motor Control Circuitry

Bridge Control

The IN1 and IN2 control pins enable the H-bridge outputs. The following table shows the logic:

Table 2. H-Bridge Logic

IN1

IN2

OUT1

OUT2

Function

0

0

Z

Z

Sleep/coast

0

1

L

H

Reverse

1

0

H

L

Forward

1

1

H

H

Brake

When both bits are zero, the output drivers are disabled and the device is placed into a low-power sleep state.

The current limit fault condition (if present) is also cleared. Note that when transitioning from either brake or sleep

mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to

the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle. Because of this, high-

speed PWM signals cannot be applied to the IN1 and IN2 pins. To control motor speed, use the VSET pin as

described below.

Because of the sleep mode functionality described previously, when applying an external PWM to the DRV8832-

Q1, hold one input logic high while applying a PWM signal to the other. If the logic input is held low instead, then

the device will cycle in and out of sleep mode, causing the FAULTn pin to pulse low on every sleep mode exit.

Voltage Regulation

The DRV8832-Q1 provides the ability to regulate the voltage applied to the motor winding. This feature allows

constant motor speed to be maintained even when operating from a varying supply voltage such as a

discharging battery.

The DRV8832-Q1 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current

consumption and maximize battery life.

Copyright © 2013–2014, Texas Instruments Incorporated

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