Switch-Mode Regulator with

+5V to ±12V or ±15V Dual Output

6

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______________________________________________________________Pin Description

Inverting Compensation Capacitor

CC-

9

Inverting Section Feedback Input

FB-

10

Current-Sense Low (inverting section)

CSL-

11

Current-Sense High (inverting section)

CSH-

12

Supply Voltage Input (+5V)

V+

13

Selects oscillator frequency. Ground for 200kHz, or tie to V+ for 100kHz.

100/200

5

12/15

6

Reference Voltage Output (+2.00V). Force to GND or V+ to disable chip.

VREF

7

Soft-Start Timing Capacitor (sources 5µA)

SS

8

Analog Supply Voltage Input (+5V)

AV+

4

Analog Ground

AGND

3

PIN

Step-Up Compensation Capacitor

CC+

2

Step-Up Feedback Input

FB+

1

FUNCTION

NAME

Charge-Pump Driver—clock output at 1/2 oscillator frequency.

PUMP

16

Push-Pull Output—drives external logic-level N-channel MOSFET.

EXT+

17

High-Current Ground

GND

18

Current-Sense Low (step-up section)

CSL+

19

Current-Sense High (step-up section)

CSH+

20

Push-Pull Output—drives external P-channel MOSFET.

EXT-

14

Voltage Input—negative supply for P-channel MOSFET driver.

PDRV

15

________________Operating Principle

Each current-mode controller consists of a summing

amplifier that adds three signals: the current waveform

from the power switch FET, an output-voltage error sig-

nal, and a ramp signal for AC compensation generated

by the oscillator. The output of the summing amplifier

resets a flip-flop, which in turn activates the power FET

driver stage (Figure 1).

Both external transistor switches are synchronized to

the oscillator and turn on simultaneously when the flip-

flop is set. The switches turn off individually when their

source currents reach a trip threshold determined by

the output-voltage error signal. This creates a duty-

cycle modulated pulse train at the oscillator frequency,

where the on time is proportional to both the output-

voltage error signal and the peak inductor current. Low

peak currents or high output-voltage error signals result

in a high duty cycle (up to 90% maximum).

AC stability is enhanced by the internal ramp signal

applied to the error amplifier. This scheme eliminates

regenerative “staircasing” of the inductor current, which

is otherwise a problem when in continuous current

mode with greater than 50% duty cycle.