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HEF4053B Datasheet(PDF) 10 Page - NXP Semiconductors |
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HEF4053B Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 20 page HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 11 — 11 September 2014 10 of 20 NXP Semiconductors HEF4053B Triple single-pole double-throw analog switch [1] For nYn to nZ or nZ to nYn propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD. Test data is given in Table 10. Definitions: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including test jig and probe. RL = Load resistance. Fig 15. Test circuit for measuring switching times 001aaj903 VI VO RT CL RL S1 DUT PULSE GENERATOR tW VM VI VI VDD VDD VSS VEE open 0 V negative pulse VI 0 V positive pulse 10 % 90 % 90 % 10 % VM VM VM tW tf tf tr tr Table 10. Test data Input Load S1 position nYn, nZ Sn and E tr, tf VM CL RL tPHL[1] tPLH tPZH, tPHZ tPZL, tPLZ other VDD or VEE VDD or VSS 20 ns 0.5VDD 50 pF 10 k VDD or VEE VEE VEE VDD VEE |
Similar Part No. - HEF4053B_15 |
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Similar Description - HEF4053B_15 |
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