SCL

SDA

Stop

70%

30%

70%

30%

Start

Start

Stop

OPT3001

SBOS681B – JULY 2014 – REVISED DECEMBER 2014

www.ti.com

6.6 Timing Requirements

(1)

MIN

TYP

MAX

UNIT

SCL operating frequency

0.01

0.4

MHz

Bus free time between stop and start

1300

ns

Hold time after repeated start

600

ns

Setup time for repeated start

600

ns

Setup time for stop

600

ns

Data hold time

20

900

ns

Data setup time

100

ns

SCL clock low period

1300

ns

SCL clock high period

600

ns

Clock rise and fall time

300

ns

Data rise and fall time

300

ns

Bus timeout period. If the SCL line is held low for this duration of time, the bus

28

ms

state machine is reset.

SCL operating frequency

0.01

2.6

MHz

Bus free time between stop and start

160

ns

Hold time after repeated start

160

ns

Setup time for repeated start

160

ns

Setup time for stop

160

ns

Data hold time

20

140

ns

Data setup time

20

ns

SCL clock low period

240

ns

SCL clock high period

60

ns

Clock rise and fall time

40

ns

Data rise and fall time

80

ns

Bus timeout period. If the SCL line is held low for this duration of time, the bus

28

ms

state machine is reset.

(1)

All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of final settled value.

6

Submit Documentation Feedback

Copyright © 2014, Texas Instruments Incorporated

Product Folder Links: OPT3001