Low-Power Dual-/Triple-Voltage SC70 µP

Supervisory Circuits

8

_______________________________________________________________________________________

Pin Description

PIN

MAX6736

MAX6737

MAX6738

MAX6739

MAX6740

MAX6743

MAX6741

MAX6744

MAX6742

MAX6745

NAME

FUNCTION

11111

RESET

Reset Output, Push-Pull or Open Drain Active Low.

RESET

changes from high to low when any monitored power-supply

threshold. It remains low until all monitored power-supply

reset timeout period.

RESET is forced low if MR is low for at

least the

MR minimum input pulse width. It remains low for

the

MR reset timeout period after MR goes high. The push-

open-drain outputs require an external pullup resistor. The

MAX6740/MAX6741/MAX6742 open-drain outputs have an

internal 50k

reset function.

22222

GND

Ground

33

———

MR

Manual Reset, Active Low. Pull low for at least

MR minimum

input pulse width to force

RESET low. Reset remains active

as long as

MR is low and for the MR reset timeout period

after

MR goes high. There is an internal 1.5k

Ω pullup resistor

4

—

44

—

Voltage Input 1. Power supply and input for the secondary

µP voltage reset monitor.

—

43

——

RSTIN

Adjustable Reset Threshold Input.

RESET is asserted when

RSTIN is below the internal 0.488V reference level. Set the

adjustable reset threshold with an external resistor-divider

55555

Voltage Input 2. Power supply and input for the primary µP

voltage reset monitor.

————

4

PFI

Power-Fail Comparator Input.

PFO is asserted when PFI is

below 0.488V.

PFO is deasserted without any reset timeout

period when PFI goes above 0.488V. Connect PFI to an

external resistor network to set the desired monitor

threshold.

————

3

PFO

Power-Fail Comparator Output, Open Drain Active Low.

PFO

is asserted when PFI is below 0.488V.

———

3

—

POK1

period. POK1 logic is independent of the

sequencing.