Full-Featured µP Supervisory Circuit with

±1.5% Reset Accuracy

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7

Pin Description

RESET has a strong pulldown but a relatively weak pullup, and can be wire-OR connected to logic gates.

RESET

9

Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watch-

generate resets during watchdog faults.

WDO

10

CE OUT

11

Chip-Enable Input

CE IN

12

Battery-On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to

BATT ON

13

Ground

GND

5

Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low

nected if not used.

MR

6

LOW LINE

7

Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks

RESET

8

Watchdog Input. If WDI remains high or low longer than the watchdog-timeout period (1.6s, typ), WDO

goes low. Leave unconnected to disable the watchdog function.

WDI

4

Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.

3

PIN

PFO

2

PFI

1

FUNCTION

NAME

BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and

BATT

14

≥ 4V.

BATT OK

15

OUT with a 0.1µF capacitor to GND.

OUT

16