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MAX807MCPE Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX807MCPE Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 16 page Full-Featured µP Supervisory Circuit with ±1.5% Reset Accuracy ______________________________________________________________________________________ 11 (see the Chip-Enable Propagation Delay vs. CE OUT Load Capacitance graph in the Typical Operating Characteristics). The CE propagation delay is produc- tion tested from the 50% point on CE IN to the 50% point on CE OUT using a 50 Ω driver and 50pF of load capacitance (Figure 8). For minimum propagation delay, minimize the capacitive load at CE OUT and use a low output-impedance driver. Chip-Enable Output In the enabled mode, the impedance of CE OUT is equiv- alent to 75 Ω in series with the source driving CE IN. In the disabled mode, the 75 Ω transmission gate is off and CE OUT is actively pulled to the higher of VCC or VBATT. This source turns off when the transmission gate is enabled. Low-Line Comparator The low-line comparator monitors VCC with a threshold voltage typically 52mV above the reset threshold, with 13mV of hysteresis. Use LOW LINE to provide a non- maskable interrupt (NMI) to the µP when power begins to fall to initiate an orderly software shutdown routine. In most battery-operated portable systems, reserve energy in the battery provides ample time to complete the shutdown routine once the low-line warning is encountered, and before reset asserts. If the system must contend with a more rapid VCC fall time—such as when the main battery is disconnected, a DC-DC converter shuts down, or a high-side switch is opened during normal operation—use capacitance on the VCC line to provide time to execute the shutdown routine (Figure 9). First calculate the worst-case time required for the system to perform its shutdown routine. Then, with the worst-case shutdown time, the worst-case load current, and the minimum low-line to reset threshold (VLR(min)), calculate the amount of capacitance required to allow the shutdown routine to complete before reset is asserted: CHOLD = (ILOAD x tSHDN) / VLR (min) where tSHDN is the time required for the system to com- plete the shutdown routine, and includes the VCC to low-line propagation delay; and where ILOAD is the cur- rent being drained from the capacitor, VLR is the low- line to reset threshold. VCC CE IN RESET THRESHOLD CE OUT RESET RESET 26 µs 28 µs 26 µs MAX807 CE IN 50pF CLOAD CE OUT GND VRST MAX 50 Ω DRIVER VCC Figure 7. Reset and Chip-Enable Timing Figure 8. CE Propagation Delay Test Circuit GND VCC TO µP NMI CHOLD CHOLD > ILOAD x tSHDN VLR 4.5V to 5.5V LOW LINE MAX807 REGULATOR Figure 9. Using LOW LINE to Provide a Power-Fail Warning to the µP |
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