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MAX807NCWE Datasheet(PDF) 9 Page - Maxim Integrated Products

Part No. MAX807NCWE
Description  Full-Featured uP Supervisory Circuit with /-1.5% Reset Accuracy
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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 9 page
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Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________
9
The RESET output is active low and implemented with a
strong pulldown/relatively weak pullup structure. It is
guaranteed to be a logic low for 0 < VCC < VRST, pro-
vided VBATT is greater than 2V. Without a backup bat-
tery, RESET is guaranteed valid for VCC
≥ 1. It typically
sinks 3.2mA at 0.1V saturation voltage in its active state.
The RESET output is the inverse of the RESET output; it
both sources and sinks current and cannot be wire-OR
connected. Figure 2a shows a timing diagram with VCC
rising and Figure 2b shows VCC falling.
Manual Reset Input
Many µP-based products require manual-reset capabil-
ity to allow an operator or test technician to initiate a
reset. The Manual Reset (MR) input permits the genera-
tion of a reset in response to a logic low from a switch,
WDO, or external circuitry. Reset remains asserted
while MR is low, and for 200ms after MR returns high.
MR has an internal 50µA to 200µA pullup current, so it
can be left open if it is not used. MR can be driven with
TTL or CMOS-logic levels, or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function;
external debounce circuitry is not required. If MR is dri-
ven from long cables or if the device is used in a noisy
environment, connect a 0.1µF capacitor from MR to
ground to provide additional noise immunity. As shown
in Figure 3, diode-ORed connections can be used to
allow manual resets from multiple sources. Figure 4
shows the reset timing.
Watchdog Timer
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within
1.6s, WDO goes low. The internal 1.6s timer is cleared
and WDO returns high when reset is asserted or when
a transition (low-to-high or high-to-low) occurs at WDI
while RESET is high. As long as reset is asserted, the
timer remains cleared and does not count. As soon as
reset is released, the timer starts counting (Figure 5).
Supply current is typically reduced by 10µA when WDI
is at a valid logic level.
VRESET
VLOW LINE
VCC
(MAX801)
VRESET
(MAX808)
VCE OUT
VRST VLL
tRP
tRP
VBATT
SHOWN FOR VCC = 0 to 5V, VBATT = 2.8V, CE IN = GND
VRESET
VLOW LINE
VCC
VRESET
VCE OUT
VRST
VRST + VLR
VBATT
SHOWN FOR VCC = 5V to 0, VBATT = 2.8V, CE IN = GND
Figure 2a. Timing Diagram, VCC Rising
Figure 2b. Timing Diagram, VCC Falling
MAX807
*
*
OTHER
RESET
SOURCES
MANUAL RESET
MR
*DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS.
Figure 3. Diode “OR” Connections Allow Multiple Reset
Sources to Connect to MR




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