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MAX807NCWE Datasheet(PDF) 10 Page - Maxim Integrated Products

Part No. MAX807NCWE
Description  Full-Featured uP Supervisory Circuit with /-1.5% Reset Accuracy
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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 10 page
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Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
10
______________________________________________________________________________________
Watchdog Output
WDO remains high if there is a transition or pulse at
WDI during the watchdog-timeout period. WDO goes
low if no transition occurs at WDI during the watchdog-
timeout period. The watchdog function is disabled and
WDO is a logic high when VCC is below the reset
threshold or WDI is an open circuit. To generate a sys-
tem reset on every watchdog fault, diode-OR connect
WDO to MR (Figure 6). When a watchdog fault occurs
in this mode, WDO goes low, which pulls MR low, caus-
ing a reset pulse to be issued. As soon as reset is
asserted, the watchdog timer clears and WDO returns
high. With WDO connected to MR, a continuous high or
low on WDI will cause 200ms reset pulses to be issued
every 1.6s.
Chip-Enable Signal Gating
The MAX807 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
the CMOS RAM in the event of a power failure. During
normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX807 uses a series
transmission gate from the Chip-Enable Input (CE IN) to
the Chip-Enable Output (CE OUT) (Figure 1).
The 8ns (max) chip-enable propagation from CE IN to
CE OUT enables the MAX807 to be used with most µPs.
Chip-Enable Input
CE IN is high impedance (disabled mode) while RESET
is asserted. During a power-down sequence when VCC
passes the reset threshold, the CE transmission gate
disables and CE IN becomes high impedance 28µs
after reset is asserted (Figure 7). During a power-up
sequence, CE IN remains high impedance (regardless
of CE IN activity) until reset is deasserted following the
reset-timeout period.
In the high-impedance mode, the leakage currents into
this input are ±1µA (max) over temperature. In the low-
impedance mode, the impedance of CE IN appears as
a 75
Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT
MR
RESET
CE IN
0V
170ns
28
µs TYP
1
µs MIN
CE OUT
VCC
VRST
RESET
tWD
WDO
WDI
WDO CONNECTED TO
µP INTERRUPT.
tRP
Figure 4. Manual-Reset Timing Diagram
Figure 5. Watchdog Timing Relationship
VCC
VCC
RESET
WDO
WDO
4.7k
TO
µP
MR
RESET
WDI
tRP
tRP
tWD
50µs
MAX807
Figure 6. Generating a Reset on Each Watchdog Fault




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