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MAX807NCWE Datasheet(PDF) 7 Page - Maxim Integrated Products

Part No. MAX807NCWE
Description  Full-Featured uP Supervisory Circuit with /-1.5% Reset Accuracy
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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 7 page
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Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________
7
Pin Description
Active-Low Reset Output. RESET is triggered and stays low when VCC is below the reset threshold or
when MR is low. It remains low 200ms after VCC rises above the reset threshold or MR returns high.
RESET has a strong pulldown but a relatively weak pullup, and can be wire-OR connected to logic gates.
Valid for VCC
≥ 1V. RESET swings between VCC and GND.
RESET
9
Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watch-
dog-timeout period (tWD), and remains low until the next transition of WDI. WDO remains high if WDI is
unconnected. WDO is high during reset. WDO swings between VCC and GND. Connect WDO to MR to
generate resets during watchdog faults.
WDO
10
Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of VCC
or VBATT, when the chip-enable gate is disabled.
CE OUT
11
Chip-Enable Input
CE IN
12
Battery-On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to
BATT and low when OUT is connected to VCC. Connect the base of a PNP transistor or gate of a PMOS
transistor to BATT ON for IOUT requirements exceeding 250mA. BATT ON swings between the higher of
VCC and VBATT and GND.
BATT ON
13
Ground
GND
5
Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low
and for 200ms after MR returns high. MR is an active-low input with an internal pullup to VCC. It can be
driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to VCC, or leave uncon-
nected if not used.
MR
6
Low-Line Comparator Output. This CMOS-logic output goes low when VCC falls to 52mV above the reset
threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when VCC is falling.
LOW LINE swings between VCC and GND.
LOW LINE
7
Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks
current. RESET swings between VCC and GND.
RESET
8
Watchdog Input. If WDI remains high or low longer than the watchdog-timeout period (1.6s, typ), WDO
goes low. Leave unconnected to disable the watchdog function.
WDI
4
Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.
VCC
3
PIN
Power-Fail Output. This CMOS-logic output goes low when PFI is less than VPFT (2.265V). Valid for
VCC
≥ 4V. PFO swings between VCC and GND.
PFO
2
Power-Fail Input. When PFI is less than VPFT (2.265V), PFO goes low. Connect to ground when unused.
PFI
1
FUNCTION
NAME
Backup-Battery Input. When VCC falls below the reset threshold and VBATT, OUT switches from VCC to
BATT. VBATT may exceed VCC. The battery can be removed while the MAX807 is powered-up, provided
BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and
connect VCC and OUT together.
BATT
14
Battery-OK Signal Output. High in normal operating mode when VBATT exceeds VBOK (2.265V). Valid for
VCC
≥ 4V.
BATT OK
15
Output Supply Voltage to CMOS RAM. When VCC exceeds the reset threshold or VCC > VBATT, OUT is
connected to VCC. When VCC falls below the reset threshold and VBATT, OUT connects to BATT. Bypass
OUT with a 0.1µF capacitor to GND.
OUT
16




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