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DRV8701 Datasheet(PDF) 3 Page - Texas Instruments |
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DRV8701 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 42 page  1 2 3 4 5 6 18 17 16 15 14 13 VM VCP CPH CPL GND VREF SH1 GH1 GND PH EN nSLEEP GND (PPAD) 1 2 3 4 5 6 18 17 16 15 14 13 VM VCP CPH CPL GND VREF SH1 GH1 GND IN1 IN2 nSLEEP GND (PPAD) DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 5 Pin Configuration and Functions RGE Package RGE Package 24-Pin VQFN 24-Pin VQFN DRV8701E Top View DRV8701P Top View DRV8701E (PH/EN) PIN TYPE DESCRIPTION NAME NO. EN 14 Input Bridge enable input Logic low places the bridge in brake mode; see Table 1 PH 15 Input Bridge phase input Controls the direction of the H-bridge; see Table 1 DRV8701P (PWM) PIN TYPE DESCRIPTION NAME NO. IN1 15 Input Bridge PWM input Logic controls the state of H-bridge; see Table 2 IN2 14 Input Common Pins PIN TYPE DESCRIPTION NAME NO. Connect to motor supply voltage; bypass to GND with a 0.1-µF VM 1 Power Power supply ceramic plus a 10-µF minimum capacitor rated for VM; additional capacitance may be required based on drive current 5 GND 16 Power Device ground Must be connected to ground PPAD VCP 2 Power Charge pump output Connect a 16-V, 1-µF ceramic capacitor to VM CPH 3 Connect a 0.1-µF X7R capacitor rated for VM between CPH and Power Charge pump switching nodes CPL CPL 4 3.3-V logic supply regulator; bypass to GND with a 6.3-V, 1-µF DVDD 8 Power Logic regulator ceramic capacitor 4.8-V analog supply regulator; bypass to GND with a 6.3-V, 1-µF AVDD 7 Power Analog regulator ceramic capacitor Pull logic low to put device into a low-power sleep mode with FETs nSLEEP 13 Input Device sleep mode High-Z; internal pulldown Resistor value or voltage forced on this pin sets the gate drive IDRIVE 12 Input Gate drive current setting pin current; see applications section for more details Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DRV8701 |
Similar Part No. - DRV8701_15 |
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Similar Description - DRV8701_15 |
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