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TAS5729MD Datasheet(PDF) 6 Page - Texas Instruments |
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TAS5729MD Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 62 page  TAS5729MD SLOS836C – MAY 2013 – REVISED MARCH 2015 www.ti.com 7.4 Thermal Information TAS5729MD THERMAL METRIC(1) DCA(2) DCA(3) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 62.6 32.6 °C/W RθJC(top) Junction-to-case (bottom) thermal resistance 17.9 16.2 °C/W RθJB Junction-to-board thermal resistance 11.9 14.4 °C/W ψJT Junction-to-top characterization parameter 0.8 0.9 °C/W ψJB Junction-to-board characterization parameter 13.5 14.3 °C/W RθJC(bottom) Junction-to-case (top) thermal resistance 1.5 1.4 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) JEDEC Standard 2 Layer Board (3) JEDEC Standard 4 Layer Board 7.5 Digital I/O Pins over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |IIH| Input logic high current level All digital pins 75 µA VIH Input logic high threshold for DVDD All digital pins 2 V referenced digital inputs |IIL| Input logic low current level All digital pins 75 µA VIL Input logic low threshold for DVDD All digital pins 0.8 V referenced digital inputs VOH Output logic high voltage level IOH = 4 mA, VDD = 3 V 2.4 V VOL Output logic low voltage level IOH = –4 mA, VDD = 3 V 0.5 V 7.6 Master Clock over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT DMCLK Allowable MCLK duty cycle 40% 50% 60% fMCLK Supported MCLK frequencies 2.8224 24.576 MHz tr Rise or fall time for MCLK 5 ns tf 7.7 Serial Audio Port over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCLK Supported SCLK frequencies Values include 32, 48, and 64 32 64 × fS DSCLK Allowable SCLK duty cycle 40% 50% 60% Required SDIN setup time before SCLK tsu2 10 ns rising edge Required SDIN hold time after SCLK rising th2 10 ns edge fS Supported input sample rates 8 48 kHz DLRCLK Allowable LRCLK duty cycle 40% 50% 60% tsu1 Required LRCLK to SCLK rising edge 10 ns th1 Required LRCLK to SCLK rising edge 10 ns tr, tf Rise or fall time for SCLK and LRCLK 8 ns Allowable LRCLK drift before LRCLK reset 4 MCLKs 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TAS5729MD |
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