General Description

The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock

driver repeats the selected LVDS or LVTTL/LVCMOS

input on two output banks. Each bank consists of seven

LVTTL/LVCMOS series terminated outputs and a bank

enable. The LVDS input has a fail-safe function. The

MAX9160 has a propagation delay that can be adjusted

using an external resistor to set the bias current for an

internal delay cell. The LVTTL/LVCMOS outputs feature

200ps maximum output-to-output skew and

±100ps maxi-

mum added peak-to-peak jitter.

The MAX9160 is designed to operate with a 3.3V sup-

ply voltage over the extended temperature range of

-40°C to +85°C. This device is available in 28-pin

exposed- and nonexposed-pad TSSOP and 32-lead

5mm x 5mm QFN packages.

Applications

Features

o LVDS or LVTTL/LVCMOS Input Selection

o LVDS Input Fail-Safe Sets Outputs High for Open,

Undriven Short, or Undriven Parallel Termination

o Two Output Banks with Separate Bank Enables

o Integrated Output Series Termination for 60Ω

Lines

o 200ps (max) Output-to-Output Skew

o ±100ps (max) Peak-to-Peak Added Output Jitter

o 42% to 58% Output Duty Cycle at 125MHz

o Guaranteed 125MHz Operating Frequency

or Open (Hot Swappable)

o 28-Pin Exposed- and Nonexposed-Pad TSSOP

or 32-Lead QFN Packages

o -40°C to +85°C Operating Temperature

o 3.0V to 3.6V Supply Voltage

LVDS or LVTTL/LVCMOS Input to

14 LVTTL/LVCMOS Output Clock Driver

________________________________________________________________ Maxim Integrated Products

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

OUTA4

OUTA3

GND

OUTA2

OUTA1

OUTB2

OUTA0

OUTB6

GND

OUTB5

OUTB4

OUTB3

OUTB1

OUTB0

ENB

RSET

GND

IN-

IN+

GND

SE_IN

SEL

ENA

OUTA6

OUTA5

TSSOP

TOP VIEW

MAX9160

Pin Configurations

Ordering Information

Function Table

19-2392; Rev 0; 4/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Typical Application Circuit and Functional Diagram appear

at end of data sheet.

PART

TEMP RANGE

PIN-PACKAGE

MAX9160EUI

-40°C to +85°C

28 TSSOP

MAX9160AEUI

-40°C to +85°C

28 TSSOP-EP**

MAX9160EGJ*

-40°C to +85°C

32 QFN-EP

H = high logic level

L = low logic level

X = don’t care

EN_

SEL

SE_IN

OUT_

HH

H

X

H

HH

L or

open

XL

H

L or

open

X

≥ +50mV

H

H

L or

open

X

≤ -50mV

L

H

L or

open

X

Open, undriven short, or

undriven parallel termination

H

L or

Open

X

XXL

Cellular Base Stations

Servers

Add/Drop Multiplexers

Digital Cross-Connects

DSLAMs

Networking Equipment

*Future product—contact factory for availability.

**Exposed pad.

Pin Configurations continued at end of data sheet.