36-44GHz Low Noise Amplifier

CHA2194

Ref : DSCHA21942035 -04-Feb.-02

9/10

Specifications subject to change without notice

Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE

Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09

Chip Biasing options

Internal DC schematic

This chip is self-biased, and flexibility is provided by the access to positive Vg.

The internal DC electrical schematic is given in order to use these pads in a safe way.

Absolute recommandations

N°1: Do not exceed Vds* = 3,5 Volt ( internal Drain to Source voltage ).

N°2: Do not bias in such a way that Vgs* becomes po sitive. (internal Gate to Source voltage)

Typical biasing table and Typical results in test Jig at 40 GHz

40GHz IN TEST Jig

Vds ( V) Vg12 (V) Vg3 (V)

Id (mA)

Typical NF(dB) Typical Gain (dB) Typical P-1dB (dB) Typical Psat (dB)

Standard

3.5

NC

NC

42

2.9

19

10

12

Low Noise High linearity

4

1

1

60

2,95

20

11

14

Low noise /low current consumption

3,5

-1

-1

30

3

17,5

8

11

Switch off

3.5

-8

-5

0

X

X

X

X