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AMC7834 Datasheet(PDF) 5 Page - Texas Instruments |
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AMC7834 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 90 page  AMC7834 www.ti.com SLAS972A – NOVEMBER 2014 – REVISED APRIL 2015 Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. GPIO1 56 I/O General-purpose digital I/Os. These pins are bidirectional open-drain, digital I/Os and GPIO2 55 I/O requires an external 10 k Ω pullup resistor to a voltage no higher than AVDD. If unused, the GPIO3 54 I/O GPIO pins should be connected to ground. GPIO4 53 I/O IO supply voltage (1.7 V to 3.6 V). This pin sets the I/O operating voltage and threshold IOVDD 12 — levels. PAVDD 41 — Power supply for the PA_ON control signal (4 V to 20 V). PA_ON is a synchronization signal capable of driving an external PMOS switch and controlling the flow of drain current to a power amplifier (PA) transistor. The PA_ON pin has an internal 120 k Ω pull-up resistor to the PAVDD pin. The maximum output voltage is set by the PAVDD pin and limited to 20 V. For drain voltages higher than 20 V, tying the PAVDD pin PA_ON 40 O to the AVDD pins and scaling the control signal externally is recommended. The PA_ON signal state can be set through a register write but it can also be configured to trigger automatically in the case of an ALARM event or when any of the SLEEP signals is activated. Reference compensation capacitor connection. Connect a 4.7 μF capacitor between this REF_CMP 42 I/O pin and the AGND4 pin for ADC reference compensation. Reference input to the device. This pin can be connected to the REF_OUT pin to use the REF_IN 20 I device internal reference or alternatively to an external voltage reference source. Internal voltage reference output. Connect this pin directly to the REF_IN pin to operate the REF_OUT 21 O device in internal reference mode. An external buffer amplifier with a high impedance input is required to drive an external load. This pin can be left unconnected. RESET 5 I Active low reset input. Logic low on this pin causes the device to perform a hardware reset. SCLK 7 I Serial interface clock. Serial interface data input. Data is clocked into the input shift register on each rising edge SDI 9 I of the SCLK pin. Serial interface data output. The SDO pin is in high impedance when the CS pin is high. SDO 10 O Data is clocked out of the input shift register on each falling edge of the SCLK pin. SENSE1+ 39 I Current sense 1 external sense resistor power connection SENSE1– 38 I Current sense 1 external sense resistor load connection SENSE2+ 37 I Current sense 2 external sense resistor power connection SENSE2– 36 I Current sense 2 external sense resistor load connection SENSE3+ 34 I Current sense 3 external sense resistor power connection SENSE3– 33 I Current sense 3 external sense resistor load connection SENSE4+ 32 I Current sense 4 external sense resistor power connection SENSE4– 31 I Current sense 4 external sense resistor load connection Active high asynchronous power down digital input 1. The power down functions of this pin SLEEP1 3 I are register configurable. Active high asynchronous power down digital input 2. The power down functions of this pin SLEEP2 4 I are register configurable. Power-on reset and clamp voltage control input for bipolar DACs 1 and 2. The resulting power-on reset (POR) and clamp voltage value is given by Equation 1. VCLAMP1 30 I CLAMP = –3 × VCLAMP[1:2] (1) Power-on reset and clamp voltage control input for bipolar DACs 3 and 4. The resulting VCLAMP2 29 I POR and clamp voltage value is given by Equation 1. The thermal pad is located on the bottom-side of the device package. The thermal pad Thermal Pad — should be tied to the same potential as the AVSS pin for optimal thermal dissipation. Alternatively, the thermal pad can be left unconnected. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: AMC7834 |
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